wind/android_kernel_modules_and_devicetree_oneplus_mt6991
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Synchronize code for OnePlus PLC110_15.0.2.501(CN01)

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Based on MTK release TAG:
alps/kernel/build/bazel_mgk_rules:t-alps-release-v0.mp1.rc-V9.12
alps/vendor/mediatek/kernel_modules/afs_common_utils:t-alps-release-v0.mp1.rc-V9.12
alps/vendor/mediatek/kernel_modules/connectivity/bt/mt66xx:t-alps-release-v0.mp1.rc-V9.12
alps/vendor/mediatek/kernel_modules/connectivity/bt/mt76xx/sdio:t-alps-release-v0.mp1.rc-V13.64
alps/vendor/mediatek/kernel_modules/connectivity/common:t-alps-release-v0.mp1.rc-V9.12
alps/vendor/mediatek/kernel_modules/connectivity/connfem:t-alps-release-v0.mp1.rc-V13.64
alps/vendor/mediatek/kernel_modules/connectivity/conninfra:t-alps-release-v0.mp1.rc-V9.12
alps/vendor/mediatek/kernel_modules/connectivity/fmradio:t-alps-release-v0.mp1.rc-V13.64
alps/vendor/mediatek/kernel_modules/connectivity/gps:t-alps-release-v0.mp1.rc-V9.12
alps/vendor/mediatek/kernel_modules/connectivity/wlan/adaptor:t-alps-release-v0.mp1.rc-V9.12
alps/vendor/mediatek/kernel_modules/connectivity/wlan/core/gen2:t-alps-release-b0.mp1.cs1-pre33
alps/vendor/mediatek/kernel_modules/connectivity/wlan/core/gen3:t-alps-release-v0.mp1.rc-V9.12
alps/vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4-mt7663:t-alps-release-b0.mp1.cs1-pre33
alps/vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4-mt7668:t-alps-release-b0.mp1.cs1-pre33
alps/vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4-mt79xx:t-alps-release-v0.mp1.rc-V13.64
alps/vendor/mediatek/kernel_modules/gpu:t-alps-release-v0.mp1.rc-V9.12
alps/vendor/mediatek/kernel_modules/hbt_driver:t-alps-release-v0.mp1.rc-V13.64
alps/vendor/mediatek/kernel_modules/hbt_driver_cus:t-alps-release-v0.mp1.rc-V13.64
alps/vendor/mediatek/kernel_modules/met_drv_v2:t-alps-release-b0.mp1.cs1-pre33
alps/vendor/mediatek/kernel_modules/met_drv_v3:t-alps-release-v0.mp1.rc-V13.64
alps/vendor/mediatek/kernel_modules/udc:t-alps-release-b0.mp1.cs1-pre33
kernel/build:t-alps-release-v0.mp1.rc-V9.12
neptune/bt_driver/linux_v2:t-alps-release-v0.mp1.rc-V9.12
neptune/wlan_driver/gen4m:t-alps-release-v0.mp1.rc-V9.12
quark/kernel_device_modules-6.6:t-alps-release-v0.mp1.rc-V9.12
quark/mtkcam-kernel_device_modules:t-alps-release-v0.mp1.rc-V9.12
This commit is contained in:
pswbuild 2025-08-20 14:23:37 +08:00
parent 0951911248
commit a06a6c87db
581 changed files with 19296 additions and 473337 deletions
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4
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/mt6991.dts
View File

@ -21838,10 +21838,6 @@ &mt6373_vbuck4_ufs {
regulator-min-microvolt = <0>;
};
&mt6373_vrfio18_aif {
regulator-always-on;
};
/delete-node/ &mt6363_vbuck1_sshub;
/delete-node/ &mt6363_vbuck2_sshub;
/delete-node/ &mt6363_vbuck4_sshub;

74
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus-display/ac262-p-7-a0014-dsi-cmd-panel-cmd.dtsi
View File

@ -130,6 +130,32 @@ timing@sa_fhd_120 {
39 00 00 40 00 00 02 38 00
39 00 00 00 00 00 03 51 00 00
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 06 01 00 87 00 00 05
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 30
39 00 00 40 00 00 02 DF 00
39 00 00 40 00 00 02 6F 36
39 00 00 40 00 00 02 DF 01
];
oplus,dsi-lhbm-pressed-icon-on-pwm-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 16 01 00 87 00 00 25
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 30
39 00 00 40 00 00 02 DF 00
39 00 00 40 00 00 02 6F 36
39 00 00 40 00 00 02 DF 01
];
oplus,dsi-adfr-min-fps-120hz-command = [
];
oplus,dsi-adfr-min-fps-60hz-command = [
@ -156,6 +182,8 @@ timing@sa_fhd_120 {
oplus,dsi-on-command-state = "dsi_lp_mode";
oplus,dsi-aod-off-command-state = "dsi_ls_mode";
oplus,dsi-panel-aod-off-insert-black-command-state = "dsi_ls_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-pwm-command-state = "dsi_hs_mode";
oplus,dsi-adfr-min-fps-120hz-command-state = "dsi_hs_mode";
oplus,dsi-adfr-min-fps-60hz-command-state = "dsi_hs_mode";
oplus,dsi-adfr-min-fps-30hz-command-state = "dsi_hs_mode";
@ -325,6 +353,22 @@ timing@sa_fhd_90 {
39 00 00 40 00 00 02 38 00
39 00 00 00 00 00 03 51 00 00
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 06 01 00 87 00 00 05
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
];
oplus,dsi-lhbm-pressed-icon-on-pwm-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 16 01 00 87 00 00 25
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
];
oplus,dsi-adfr-min-fps-90hz-command = [
];
oplus,dsi-adfr-min-fps-45hz-command = [
@ -351,6 +395,8 @@ timing@sa_fhd_90 {
oplus,dsi-on-command-state = "dsi_lp_mode";
oplus,dsi-aod-off-command-state = "dsi_ls_mode";
oplus,dsi-panel-aod-off-insert-black-command-state = "dsi_ls_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-pwm-command-state = "dsi_hs_mode";
oplus,dsi-adfr-min-fps-90hz-command-state = "dsi_hs_mode";
oplus,dsi-adfr-min-fps-45hz-command-state = "dsi_hs_mode";
oplus,dsi-adfr-min-fps-30hz-command-state = "dsi_hs_mode";
@ -520,6 +566,32 @@ timing@sa_fhd_60 {
39 00 00 40 00 00 02 38 00
39 00 00 00 00 00 03 51 00 00
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 06 01 00 87 00 00 05
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 30
39 00 00 40 00 00 02 DF 02
39 00 00 40 00 00 02 6F 36
39 00 00 40 00 00 02 DF 03
];
oplus,dsi-lhbm-pressed-icon-on-pwm-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 16 01 00 87 00 00 25
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 30
39 00 00 40 00 00 02 DF 02
39 00 00 40 00 00 02 6F 36
39 00 00 40 00 00 02 DF 03
];
oplus,dsi-adfr-min-fps-60hz-command = [
];
oplus,dsi-adfr-min-fps-30hz-command = [
@ -544,6 +616,8 @@ timing@sa_fhd_60 {
oplus,dsi-on-command-state = "dsi_lp_mode";
oplus,dsi-aod-off-command-state = "dsi_ls_mode";
oplus,dsi-panel-aod-off-insert-black-command-state = "dsi_ls_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-pwm-command-state = "dsi_hs_mode";
oplus,dsi-adfr-min-fps-60hz-command-state = "dsi_hs_mode";
oplus,dsi-adfr-min-fps-30hz-command-state = "dsi_hs_mode";
oplus,dsi-adfr-min-fps-20hz-command-state = "dsi_hs_mode";

18
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus-display/ac262-p-7-a0014-dsi-cmd-panel-common.dtsi
View File

@ -57,22 +57,6 @@
39 00 00 40 00 00 02 6F 4A
39 00 00 00 00 00 05 B8 00 00 00 00
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 06 01 00 87 00 00 05
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
];
oplus,dsi-lhbm-pressed-icon-on-pwm-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 16 01 00 87 00 00 25
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
];
oplus,dsi-lhbm-pressed-icon-off-command = [
39 00 00 40 00 00 02 87 20
39 00 00 40 00 00 06 F0 55 AA 52 08 04
@ -121,8 +105,6 @@
oplus,dsi-ultra-low-power-aod-on-command-state = "dsi_ls_mode";
oplus,dsi-aod-high-mode-command-state = "dsi_ls_mode";
oplus,dsi-aod-low-mode-command-state = "dsi_ls_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-pwm-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-off-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-gamma-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-grayscale-command-state = "dsi_hs_mode";

704
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus-display/ac302-p-3-a0026-dsi-vdo-panel-cmd.dtsi
View File

@ -1,704 +0,0 @@
&ac302_p_3_a0026_dsi_vdo_panel {
oplus,dsi-display-panel@0 {
reg = <0>;
oplus,dsi-vendor-name = "A0026";
oplus,dsi-manufacture = "P_3";
oplus,dsi-display-timings {
timing@sa_fhd_120 {
cell-index = <0>;
oplus,dsi-panel-framerate = <120>;
oplus,dsi-panel-pllclk = <553>;
oplus,cmd-null-pkt-en = <0>;
oplus,cmd-null-pkt-len = <0>;
oplus,vdo-per-frame-lp-enable = <1>;
/* OPLUS_FEATURE_DISPLAY_ONSCREENFINGERPRINT */
//oplus,ofp_need_keep_apart_backlight;
#include "ac302-p-3-a0026-dsi-vdo-panel-common.dtsi"
oplus,dsi-timing-switch-command = [ // 120Hz DC(1pulse) to Normal(3+18pulse)
//15 00 00 00 00 00 02 2F 01
];
oplus,dsi-pwm-switch-1to3pul-command = [ // 120Hz DC(1pulse) to Normal(3pulse)
];
oplus,dsi-pwm-switch-1to18pul-command = [ // 120Hz DC(1pulse) to Normal(18pulse)
];
oplus,dsi-pwm-switch-18to3pul-command = [
];
oplus,dsi-pwm-switch-18to3pul-wake-command = [
];
oplus,dsi-pwm-switch-3to18pul-command = [
];
oplus,dsi-timing-switch-1pulse-command = [ // 120Hz Normal(3+18pulse) to DC(1pulse)
];
oplus,dsi-pwm-switch-3to1pul-command = [ // 120Hz Normal(3+18pulse) to DC(1pulse)
];
oplus,dsi-pwm-switch-18to1pul-command = [ // 120Hz Normal(3+18pulse) to DC(1pulse)
];
oplus,dsi-on-command = [
//DVDD Strong to 1v
//For other setting refer OP manual Ch 4.9
39 00 00 40 00 00 06 F0 55 AA 52 08 01
39 00 00 40 00 00 02 6F 03
39 00 00 40 00 00 02 C5 00
39 00 00 40 00 00 02 6F 04
39 00 00 00 00 00 04 C5 25 25 25
//VGXP by pad cap
39 00 00 40 00 00 05 FF AA 55 A5 80
39 00 00 40 00 00 02 6F 1F
39 00 00 40 00 00 02 F4 0B
39 00 00 40 00 00 02 6F 20
39 00 00 40 00 00 02 F4 3F
39 00 00 40 00 00 02 6F 08
39 00 00 40 00 00 02 FC 03
39 00 00 40 00 00 05 FF AA 55 A5 80
39 00 00 40 00 00 02 6F 24
39 00 00 00 00 00 02 F8 FF
//706A改善ESD
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 0F
39 00 00 40 00 00 02 D8 42
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F D4
39 00 00 40 00 00 02 BA 20
39 00 00 40 00 00 06 F0 55 AA 52 08 03
39 00 00 40 00 00 02 C6 87
// For Idle enter BIST
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 C0 00
39 00 00 40 00 00 06 F0 55 AA 52 08 01
39 00 00 40 00 00 02 6F 0B
39 00 00 40 00 00 02 D2 00
39 00 00 40 00 00 05 FF AA 55 A5 84
39 00 00 40 00 00 02 6F 10
39 00 00 40 00 00 02 F8 02
39 00 00 40 00 00 05 FF AA 55 A5 84
39 00 00 40 00 00 02 F2 15
//FOD OFF
39 00 00 40 00 00 06 F0 55 AA 52 08 09
39 00 00 40 00 00 02 6F 00
39 00 00 40 00 00 02 B0 01
39 00 00 40 00 00 02 6F 25
39 00 00 40 00 00 02 B0 00
39 00 00 00 00 00 02 87 00
39 00 00 40 00 00 02 6F 01
39 00 00 40 00 00 02 8B 00
//Resolution Setting
39 00 00 40 00 00 05 2A 00 00 04 FF
39 00 00 40 00 00 05 2B 00 00 0A EF
//VESA1.2 10 bit 3.75 DSC Setting
// For other refer OP manual Ch 4.4
39 00 00 40 00 00 02 90 03
39 00 00 40 00 00 02 6F 01
39 00 00 40 00 00 02 90 43
39 00 00 40 00 00 13 91 AB A8 00 28 D2 00 02 5C 04 06 00 08 02 AB 02 20 10 E0
//Dimming OFF
39 00 00 40 00 00 02 53 20
//Video Mode Ext_VFP VBPF Setting
39 00 00 40 00 00 11 3B 00 1C 00 58 00 1C 00 54 00 1C 04 0C 00 1C 0B B4
39 00 00 40 00 00 02 6F 10
39 00 00 40 00 00 05 3B 00 1C 00 54
//DPC Temperature Setting
39 00 00 40 00 00 03 81 01 19
//FPR1 EN
39 00 00 40 00 00 02 88 01
//120Hz Sleep Out
//For other refer OP manual Ch 5.4.3
39 00 00 40 00 00 02 2F 01
//TE ON
39 00 00 40 00 00 02 35 00
//Setting Loading Effect x1.0
39 00 00 40 00 00 03 5F 00 00
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 03
39 00 00 40 00 00 02 B5 D5
/*lhbm brightness*/
39 00 00 40 00 00 06 F0 55 AA 52 08 00
15 00 00 40 00 00 02 6F 25
39 00 00 40 00 00 07 DF 38 FC 38 FC 38 FC
// Sleep out
05 00 00 00 78 00 01 11
// Display out
05 00 00 00 00 00 01 29
];
oplus,dsi-timing-switch-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-1to3pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-1to18pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-18to3pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-18to3pul-wake-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-3to18pul-command-state = "dsi_hs_mode";
oplus,dsi-timing-switch-1pulse-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-3to1pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-18to1pul-command-state = "dsi_hs_mode";
oplus,dsi-on-command-state = "dsi_lp_mode";
oplus,dsc-params-entries = <&dsc_params>;
// oplus,phy-timcon {
// hs-trail = <14>;
// clk-trail = <15>;
// };
oplus,dyn-fps {
switch_en = <1>;
vact_timing_fps = <120>;
dyn_fps_data_rate;
oplus_dyn_fps_dfps_cmd_table0 = [00 02 2F 01];
};
oplus,display-mode {
display-mode@0 {
hdisplay = <1280>;
vdisplay = <2800>;
fhd-hfp = <60>;
fhd-hsa = <4>;
fhd-hbp = <35>;
fhd-vfp = <84>;
fhd-vsa = <2>;
fhd-vbp = <26>;
hskew = <STANDARD_ADFR>;
};
display-mode@1 {
hdisplay = <1080>;
vdisplay = <2363>;
fhd-hfp = <60>;
fhd-hsa = <4>;
fhd-hbp = <35>;
fhd-vfp = <84>;
fhd-vsa = <2>;
fhd-vbp = <26>;
hskew = <STANDARD_ADFR>;
};
};
};
timing@sa_fhd_90 {
cell-index = <1>;
oplus,dsi-panel-framerate = <90>;
oplus,dsi-panel-pllclk = <553>;
oplus,cmd-null-pkt-en = <0>;
oplus,cmd-null-pkt-len = <0>;
oplus,vdo-per-frame-lp-enable = <1>;
/* OPLUS_FEATURE_DISPLAY_ONSCREENFINGERPRINT */
//oplus,ofp_need_keep_apart_backlight;
#include "ac302-p-3-a0026-dsi-vdo-panel-common.dtsi"
oplus,dsi-timing-switch-command = [ // 90Hz DC(1pulse) to Normal(3+18pulse)
//15 00 00 00 00 00 02 2F 02
];
oplus,dsi-pwm-switch-1to3pul-command = [ // 90Hz DC(1pulse) to Normal(3pulse)
];
oplus,dsi-pwm-switch-1to18pul-command = [ // 90Hz DC(1pulse) to Normal(18pulse)
];
oplus,dsi-pwm-switch-18to3pul-command = [
];
oplus,dsi-pwm-switch-18to3pul-wake-command = [
];
oplus,dsi-pwm-switch-3to18pul-command = [
];
oplus,dsi-timing-switch-1pulse-command = [ // 90Hz Normal(3+18pulse) to DC(1pulse)
];
oplus,dsi-pwm-switch-3to1pul-command = [ // 90Hz Normal(3+18pulse) to DC(1pulse)
];
oplus,dsi-pwm-switch-18to1pul-command = [ // 90Hz Normal(3+18pulse) to DC(1pulse)
];
oplus,dsi-on-command = [
//DVDD Strong to 1v
//For other setting refer OP manual Ch 4.9
39 00 00 40 00 00 06 F0 55 AA 52 08 01
39 00 00 40 00 00 02 6F 03
39 00 00 40 00 00 02 C5 00
39 00 00 40 00 00 02 6F 04
39 00 00 00 00 00 04 C5 25 25 25
//VGXP by pad cap
39 00 00 40 00 00 05 FF AA 55 A5 80
39 00 00 40 00 00 02 6F 1F
39 00 00 40 00 00 02 F4 0B
39 00 00 40 00 00 02 6F 20
39 00 00 40 00 00 02 F4 3F
39 00 00 40 00 00 02 6F 08
39 00 00 40 00 00 02 FC 03
39 00 00 40 00 00 05 FF AA 55 A5 80
39 00 00 40 00 00 02 6F 24
39 00 00 00 00 00 02 F8 FF
//706A改善ESD
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 0F
39 00 00 40 00 00 02 D8 42
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F D4
39 00 00 40 00 00 02 BA 20
39 00 00 40 00 00 06 F0 55 AA 52 08 03
39 00 00 40 00 00 02 C6 87
// For Idle enter BIST
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 C0 00
39 00 00 40 00 00 06 F0 55 AA 52 08 01
39 00 00 40 00 00 02 6F 0B
39 00 00 40 00 00 02 D2 00
39 00 00 40 00 00 05 FF AA 55 A5 84
39 00 00 40 00 00 02 6F 10
39 00 00 40 00 00 02 F8 02
39 00 00 40 00 00 05 FF AA 55 A5 84
39 00 00 40 00 00 02 F2 15
//FOD OFF
39 00 00 40 00 00 06 F0 55 AA 52 08 09
39 00 00 40 00 00 02 6F 00
39 00 00 40 00 00 02 B0 01
39 00 00 40 00 00 02 6F 25
39 00 00 40 00 00 02 B0 00
39 00 00 00 00 00 02 87 00
39 00 00 40 00 00 02 6F 01
39 00 00 40 00 00 02 8B 00
//Resolution Setting
39 00 00 40 00 00 05 2A 00 00 04 FF
39 00 00 40 00 00 05 2B 00 00 0A EF
//VESA1.2 10 bit 3.75 DSC Setting
// For other refer OP manual Ch 4.4
39 00 00 40 00 00 02 90 03
39 00 00 40 00 00 02 6F 01
39 00 00 40 00 00 02 90 43
39 00 00 40 00 00 13 91 AB A8 00 28 D2 00 02 5C 04 06 00 08 02 AB 02 20 10 E0
//Dimming OFF
39 00 00 40 00 00 02 53 20
//Video Mode Ext_VFP VBPF Setting
39 00 00 40 00 00 11 3B 00 1C 00 58 00 1C 00 54 00 1C 04 0C 00 1C 0B B4
39 00 00 40 00 00 02 6F 10
39 00 00 40 00 00 05 3B 00 1C 00 54
//DPC Temperature Setting
39 00 00 40 00 00 03 81 01 19
//FPR1 EN
39 00 00 40 00 00 02 88 01
//90Hz Sleep Out
//For other refer OP manual Ch 5.4.3
39 00 00 40 00 00 02 2F 02
//TE ON
39 00 00 40 00 00 02 35 00
//Setting Loading Effect x1.0
39 00 00 40 00 00 03 5F 00 00
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 03
39 00 00 40 00 00 02 B5 D5
/*lhbm brightness*/
39 00 00 40 00 00 06 F0 55 AA 52 08 00
15 00 00 40 00 00 02 6F 25
39 00 00 40 00 00 07 DF 38 FC 38 FC 38 FC
// Sleep out
05 00 00 00 78 00 01 11
// Display out
05 00 00 00 00 00 01 29
];
oplus,dsi-timing-switch-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-1to3pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-1to18pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-18to3pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-18to3pul-wake-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-3to18pul-command-state = "dsi_hs_mode";
oplus,dsi-timing-switch-1pulse-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-3to1pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-18to1pul-command-state = "dsi_hs_mode";
oplus,dsi-on-command-state = "dsi_lp_mode";
oplus,dsc-params-entries = <&dsc_params>;
// oplus,phy-timcon {
// hs-trail = <14>;
// clk-trail = <15>;
// };
oplus,dyn-fps {
switch_en = <1>;
vact_timing_fps = <90>;
dyn_fps_data_rate;
oplus_dyn_fps_dfps_cmd_table0 = [00 02 2F 02];
};
oplus,display-mode {
display-mode@0 {
hdisplay = <1280>;
vdisplay = <2800>;
fhd-hfp = <60>;
fhd-hsa = <4>;
fhd-hbp = <35>;
fhd-vfp = <1036>;
fhd-vsa = <2>;
fhd-vbp = <26>;
hskew = <STANDARD_ADFR>;
};
display-mode@1 {
hdisplay = <1080>;
vdisplay = <2363>;
fhd-hfp = <60>;
fhd-hsa = <4>;
fhd-hbp = <35>;
fhd-vfp = <1036>;
fhd-vsa = <2>;
fhd-vbp = <26>;
hskew = <STANDARD_ADFR>;
};
};
};
timing@sa_fhd_60 {
cell-index = <2>;
oplus,dsi-panel-framerate = <60>;
oplus,dsi-panel-pllclk = <553>;
oplus,cmd-null-pkt-en = <0>;
oplus,cmd-null-pkt-len = <0>;
oplus,vdo-per-frame-lp-enable = <1>;
/* OPLUS_FEATURE_DISPLAY_ONSCREENFINGERPRINT */
//oplus,ofp_need_keep_apart_backlight;
#include "ac302-p-3-a0026-dsi-vdo-panel-common.dtsi"
oplus,dsi-timing-switch-command = [ // 60Hz DC(1pulse) to Normal(3+18pulse)
//15 00 00 00 00 00 02 2F 03
];
oplus,dsi-pwm-switch-1to3pul-command = [ // 60Hz DC(1pulse) to Normal(3pulse)
];
oplus,dsi-pwm-switch-1to18pul-command = [ // 60Hz DC(1pulse) to Normal(18pulse)
];
oplus,dsi-pwm-switch-18to3pul-command = [
];
oplus,dsi-pwm-switch-18to3pul-wake-command = [
];
oplus,dsi-pwm-switch-3to18pul-command = [
];
oplus,dsi-timing-switch-1pulse-command = [ // 60Hz Normal(3+18pulse) to DC(1pulse)
];
oplus,dsi-pwm-switch-3to1pul-command = [ // 60Hz Normal(3+18pulse) to DC(1pulse)
];
oplus,dsi-pwm-switch-18to1pul-command = [ // 60Hz Normal(3+18pulse) to DC(1pulse)
];
oplus,dsi-on-command = [
//DVDD Strong to 1v
//For other setting refer OP manual Ch 4.9
39 00 00 40 00 00 06 F0 55 AA 52 08 01
39 00 00 40 00 00 02 6F 03
39 00 00 40 00 00 02 C5 00
39 00 00 40 00 00 02 6F 04
39 00 00 00 00 00 04 C5 25 25 25
//VGXP by pad cap
39 00 00 40 00 00 05 FF AA 55 A5 80
39 00 00 40 00 00 02 6F 1F
39 00 00 40 00 00 02 F4 0B
39 00 00 40 00 00 02 6F 20
39 00 00 40 00 00 02 F4 3F
39 00 00 40 00 00 02 6F 08
39 00 00 40 00 00 02 FC 03
39 00 00 40 00 00 05 FF AA 55 A5 80
39 00 00 40 00 00 02 6F 24
39 00 00 00 00 00 02 F8 FF
//706A改善ESD
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 0F
39 00 00 40 00 00 02 D8 42
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F D4
39 00 00 40 00 00 02 BA 20
39 00 00 40 00 00 06 F0 55 AA 52 08 03
39 00 00 40 00 00 02 C6 87
// For Idle enter BIST
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 C0 00
39 00 00 40 00 00 06 F0 55 AA 52 08 01
39 00 00 40 00 00 02 6F 0B
39 00 00 40 00 00 02 D2 00
39 00 00 40 00 00 05 FF AA 55 A5 84
39 00 00 40 00 00 02 6F 10
39 00 00 40 00 00 02 F8 02
39 00 00 40 00 00 05 FF AA 55 A5 84
39 00 00 40 00 00 02 F2 15
//FOD OFF
39 00 00 40 00 00 06 F0 55 AA 52 08 09
39 00 00 40 00 00 02 6F 00
39 00 00 40 00 00 02 B0 01
39 00 00 40 00 00 02 6F 25
39 00 00 40 00 00 02 B0 00
39 00 00 00 00 00 02 87 00
39 00 00 40 00 00 02 6F 01
39 00 00 40 00 00 02 8B 00
//Resolution Setting
39 00 00 40 00 00 05 2A 00 00 04 FF
39 00 00 40 00 00 05 2B 00 00 0A EF
//VESA1.2 10 bit 3.75 DSC Setting
// For other refer OP manual Ch 4.4
39 00 00 40 00 00 02 90 03
39 00 00 40 00 00 02 6F 01
39 00 00 40 00 00 02 90 43
39 00 00 40 00 00 13 91 AB A8 00 28 D2 00 02 5C 04 06 00 08 02 AB 02 20 10 E0
//Dimming OFF
39 00 00 40 00 00 02 53 20
//Video Mode Ext_VFP VBPF Setting
39 00 00 40 00 00 11 3B 00 1C 00 58 00 1C 00 54 00 1C 04 0C 00 1C 0B B4
39 00 00 40 00 00 02 6F 10
39 00 00 40 00 00 05 3B 00 1C 00 54
//DPC Temperature Setting
39 00 00 40 00 00 03 81 01 19
//FPR1 EN
39 00 00 40 00 00 02 88 01
//120Hz Sleep Out
//For other refer OP manual Ch 5.4.3
39 00 00 40 00 00 02 2F 03
//TE ON
39 00 00 40 00 00 02 35 00
//Setting Loading Effect x1.0
39 00 00 40 00 00 03 5F 00 00
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 03
39 00 00 40 00 00 02 B5 D5
/*lhbm brightness*/
39 00 00 40 00 00 06 F0 55 AA 52 08 00
15 00 00 40 00 00 02 6F 25
39 00 00 40 00 00 07 DF 38 FC 38 FC 38 FC
// Sleep out
05 00 00 00 78 00 01 11
// Display out
05 00 00 00 00 00 01 29
];
oplus,dsi-timing-switch-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-1to3pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-1to18pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-18to3pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-18to3pul-wake-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-3to18pul-command-state = "dsi_hs_mode";
oplus,dsi-timing-switch-1pulse-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-3to1pul-command-state = "dsi_hs_mode";
oplus,dsi-pwm-switch-18to1pul-command-state = "dsi_hs_mode";
oplus,dsi-on-command-state = "dsi_lp_mode";
oplus,dsc-params-entries = <&dsc_params>;
// oplus,phy-timcon {
// hs-trail = <14>;
// clk-trail = <15>;
// };
oplus,dyn-fps {
switch_en = <1>;
vact_timing_fps = <60>;
dyn_fps_data_rate;
oplus_dyn_fps_dfps_cmd_table0 = [00 02 2F 03];
};
oplus,display-mode {
display-mode@0 {
hdisplay = <1280>;
vdisplay = <2800>;
fhd-hfp = <60>;
fhd-hsa = <4>;
fhd-hbp = <35>;
fhd-vfp = <2996>;
fhd-vsa = <2>;
fhd-vbp = <26>;
hskew = <STANDARD_ADFR>;
};
display-mode@1 {
hdisplay = <1080>;
vdisplay = <2363>;
fhd-hfp = <60>;
fhd-hsa = <4>;
fhd-hbp = <35>;
fhd-vfp = <2996>;
fhd-vsa = <2>;
fhd-vbp = <26>;
hskew = <STANDARD_ADFR>;
};
};
};
};
oplus,vdo-aod-params {
oplus,vdo-aod-mode@0{
porch_change_flag = <0x03>;
dst-hfp = <1637>;
dst-vfp = <84>;
oplus-vdo-aod-cmd-table0 = [01 39];
oplus-vdo-aod-cmd-table1 = [02 6F 04];
oplus-vdo-aod-cmd-table2 = [03 51 0F FE];
};
oplus,vdo-aod-mode@1{ //120hz
porch_change_flag = <0x03>;
dst-hfp = <60>;
dst-vfp = <84>;
oplus-vdo-aod-cmd-table0 = [01 38];
};
oplus,vdo-aod-mode@2{ //90hz
porch_change_flag = <0x03>;
dst-hfp = <60>;
dst-vfp = <1036>;
oplus-vdo-aod-cmd-table0 = [01 38];
};
oplus,vdo-aod-mode@3{ //60hz
porch_change_flag = <0x03>;
dst-hfp = <60>;
dst-vfp = <2996>;
oplus-vdo-aod-cmd-table0 = [01 38];
};
};
};
};
&ac302_p_3_a0026_dsi_vdo_panel {
oplus,dsi-display-panel@0 {
res-switch = <2>;
/* Hardware config */
oplus,panel-supply-entries = <&dsi_panel_pwr_supply>;
oplus,panel-power-on-sequence = "1", "vddio", "5", "vddr", "5", "vci", "2";
oplus,panel-power-off-sequence = "6", "vci", "6", "vddr", "6", "vddio", "1";
reset-gpios = <&pio 41 0>;
oplus,panel-reset-sequence = <2 10>, <1 1>, <0 1>, <1 26>;
/* Panel config */
oplus,dsi-serial-number-enabled = <1>;
oplus,dsi-serial-number-switch-page;
oplus,dsi-serial-number-index = <0>;
oplus,dsi-serial-number-switch-page-command = <0xF0 0x55 0xAA 0x52 0x08 0x01>;
oplus,dsi-serial-number-default-switch-page-command = <0xF0 0x55 0xAA 0x52 0x08 0x00>;
oplus,dsi-serial-number-reg = <0xD7>;
oplus,dsi-serial-number-read-count = <7>;
oplus,backlight-check-disable;
// oplus,dsi-serial-number-year-offset = <0>;
/*color*/
oplus,color-vivid-status;
//oplus,color-srgb-status;
// oplus,color-softiris-status;
// oplus,color-dual-panel-status;
//oplus,color-dual-brightness-status;
//oplus,color-oplus-calibrate-status;
// oplus,color-samsung-status;
//oplus,color-loading-status;
//oplus,color-2nit-status;
// oplus,color-nature-profession-status;
/* ESD */
oplus,cust-esd-check = <1>;
oplus,esd-check-enable = <1>;
oplus,esd_check_cmd = [
0A
AB
0D
];
oplus,esd_check_count = [
01
02
01
];
oplus,esd_check_value = [
9C
00 00
00
];
oplus,esd_check_mask = [
FF
07 0F
];
/* MIPI error check config */
/*
** BIT(0): enable/disable check
** BIT(1): enable/disable page switch
*/
// oplus,mipi-err-check-config = <0x01>; // 0b0000'0111
// oplus,mipi-err-check-reg = [
// AB
// ];
// oplus,mipi-err-check-value = [
// 00 00
// ];
// oplus,mipi-err-check-count = [
// 02
// ];
/* 32-bit binary flag
** Bit value identified how to match the return value of each register.
** The value 0(default) means equal, and the value 1 means not equal.
*/
oplus,mipi-err-check-match-modes = <0x00000000>;
/* ext_params */
oplus,panel-type = <0>;
oplus,keep_ulps = <1>;
oplus,lane-swap-en = <0>;
oplus,lane-swap = <
MIPITX_PHY_LANE_0 MIPITX_PHY_LANE_1 MIPITX_PHY_LANE_3 MIPITX_PHY_LANE_2 MIPITX_PHY_LANE_CK MIPITX_PHY_LANE_RX
MIPITX_PHY_LANE_0 MIPITX_PHY_LANE_1 MIPITX_PHY_LANE_3 MIPITX_PHY_LANE_2 MIPITX_PHY_LANE_CK MIPITX_PHY_LANE_RX
>;
oplus,lcm-color-mode = <MTK_DRM_COLOR_MODE_DISPLAY_P3>;
oplus,output-mode = <MTK_PANEL_DSC_SINGLE_PORT>;
oplus,panel-bpp = <10>;
oplus,physical-width-um = <71000>;
oplus,physical-height-um = <156000>;
oplus,vdo-per-frame-lp-enable = <1>;
oplus,change_fps_by_vfp_send_cmd = <1>;
/* OFP config */
oplus,ofp-fp-type = <0xA10>;
oplus,ofp-fp-local-hbm-calibration;
oplus,ofp-video-mode-30hz-aod-accelerate;
/*pwm config*/
oplus,pwm-turbo-support = <1>;
oplus,pwm-switch-backlight-threshold = <1162>;
oplus,pwm-aid-switch-enable;
oplus,pwm-onepulse-support = <0>;
oplus,pwm-onepulse-enabled = <0>;
oplus,pwm-turbo-wait-te = <1>;
};
};

86
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus-display/ac302-p-3-a0026-dsi-vdo-panel-common.dtsi
View File

@ -1,86 +0,0 @@
oplus,dsi-on-post-command = [
];
oplus,dsi-off-command = [
39 00 00 00 0A 00 01 28
39 00 00 00 78 00 01 10
];
oplus,dsi-set-backlight-command = [
39 00 00 00 00 00 03 51 00 00
];
oplus,dsi-aod-on-command = [
//39 00 00 00 00 00 02 39 00
39 00 00 00 00 00 03 51 03 B6
];
oplus,dsi-aod-off-command = [
//39 00 00 00 00 00 02 38 00
];
oplus,dsi-ultra-low-power-aod-on-command = [
//39 00 00 40 00 00 04 FF 5A A5 2D
//39 00 00 40 00 00 03 8A 1D 00
//39 00 00 00 00 00 04 FF 5A A5 00
];
oplus,dsi-ultra-low-power-aod-off-command = [
//39 00 00 40 00 00 04 FF 5A A5 2D
//39 00 00 40 00 00 03 8A 00 00
//39 00 00 00 00 00 04 FF 5A A5 00
];
oplus,dsi-aod-high-mode-command = [
39 00 00 40 00 00 02 6F 04
39 00 00 00 00 00 03 51 0F FE
];
oplus,dsi-aod-low-mode-command = [
39 00 00 40 00 00 02 6F 04
39 00 00 00 00 00 03 51 0D BB
];
oplus,dsi-lhbm-pressed-icon-gamma-command = [
];
oplus,dsi-lhbm-pressed-icon-grayscale-command = [
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 07 A9 01 00 2F 00 00 01
39 00 00 40 00 00 35 A9 02 08 B1 00 00 03 02 08 C1 00 07 8E 90 EE 90 90 EE 90 90 02 08 C1 08 0A EE D0 D0 02 01 B9 1D 1D 08 02 09 B0 00 00 11 01 00 8B 00 01 10 01 01 00 87 00 00 25
39 00 00 00 00 00 2E A9 01 00 A2 00 27 03 02 08 C1 00 07 8E FF EE FF FF EE FF FF 02 08 C1 08 0A EE FF FF 00 00 00 00 00 02 01 B9 1D 1D 08 00 00 00 00 00 00 00
];
oplus,dsi-lhbm-pressed-icon-off-command = [
39 00 00 40 00 00 35 A9 02 08 B1 00 00 02 02 08 C1 00 07 8F 50 FF 50 50 FF 50 50 02 08 C1 08 0A FF 50 50 02 01 B9 1D 1D 08 02 09 B0 00 00 01 01 00 8B 00 01 00 00 01 00 87 00 00 00
39 00 00 00 00 00 2E A9 01 00 A2 00 27 03 02 08 C1 00 07 8E FF EE FF FF EE FF FF 02 08 C1 08 0A EE FF FF 00 00 00 00 00 02 01 B9 1D 1D 08 00 00 00 00 00 00 00
];
oplus,dsi-switch-hbm-apl-on-command = [
];
oplus,dsi-switch-hbm-apl-off-command = [
];
oplus,dsi-hbm-on-command = [
];
oplus,dsi-hbm-off-command = [
];
oplus,dsi-set-seed-natural-command = [
15 00 00 00 00 00 02 5F 03
];
oplus,dsi-set-seed-vivid-command = [
15 00 00 00 00 00 02 5F 05
];
oplus,dsi-set-seed-expert-command = [
15 00 00 00 00 00 02 5F 00
];
oplus,dsi-on-post-command-state = "dsi_lp_mode";
oplus,dsi-off-command-state = "dsi_lp_mode";
oplus,dsi-set-backlight-command-state = "dsi_ls_mode";
oplus,dsi-aod-on-command-state = "dsi_ls_mode";
oplus,dsi-aod-off-command-state = "dsi_ls_mode";
oplus,dsi-ultra-low-power-aod-off-command-state = "dsi_ls_mode";
oplus,dsi-ultra-low-power-aod-on-command-state = "dsi_ls_mode";
oplus,dsi-aod-high-mode-command-state = "dsi_ls_mode";
oplus,dsi-aod-low-mode-command-state = "dsi_ls_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_ls_mode";
oplus,dsi-lhbm-pressed-icon-off-command-state = "dsi_ls_mode";
oplus,dsi-lhbm-pressed-icon-gamma-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-grayscale-command-state = "dsi_hs_mode";
oplus,dsi-switch-hbm-apl-on-command-state = "dsi_hs_mode";
oplus,dsi-switch-hbm-apl-off-command-state = "dsi_hs_mode";
oplus,dsi-hbm-on-command-state = "dsi_hs_mode";
oplus,dsi-hbm-off-command-state = "dsi_hs_mode";
oplus,dsi-set-seed-natural-command-state = "dsi_ls_mode";
oplus,dsi-set-seed-vivid-command-state = "dsi_ls_mode";
oplus,dsi-set-seed-expert-command-state = "dsi_ls_mode";

1
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus-display/mt6991-emira-24813-display-overlay.dtsi
View File

@ -29,6 +29,7 @@ &dsi0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
cpu-num = <3>;
/* choose second panel which support spr */
//switch-spr = <1>;
/* choose MTK SPR IP */

18
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus-display/panel-aa599-p-7-a0014-dsi-cmd-common.dtsi
View File

@ -27,22 +27,6 @@
15 00 00 40 00 00 02 6F 4A
39 00 00 00 00 00 05 B8 00 00 00 00
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
15 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 06 01 00 87 00 00 05
39 00 00 40 00 00 06 F0 55 AA 52 08 04
15 00 00 40 00 00 02 CB 37
15 00 00 00 00 00 02 8B 10
];
oplus,dsi-lhbm-pressed-icon-on-pwm-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
15 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 16 01 00 87 00 00 25
39 00 00 40 00 00 06 F0 55 AA 52 08 04
15 00 00 40 00 00 02 CB 37
15 00 00 00 00 00 02 8B 10
];
oplus,dsi-lhbm-pressed-icon-off-command = [
15 00 00 40 00 00 02 87 20
39 00 00 40 00 00 06 F0 55 AA 52 08 04
@ -105,8 +89,6 @@
oplus,dsi-aod-on-command-state = "dsi_ls_mode";
oplus,dsi-aod-high-mode-command-state = "dsi_ls_mode";
oplus,dsi-aod-low-mode-command-state = "dsi_ls_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-pwm-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-off-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-gamma-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-grayscale-command-state = "dsi_hs_mode";

109
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus-display/panel-aa599-p-7-a0014-dsi-cmd.dtsi
View File

@ -150,6 +150,32 @@ timing@sa_fhd_120 {
oplus,dsi-hbm-off-command = [
39 00 00 00 00 00 03 51 0D BB
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 06 01 00 87 00 00 05
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 30
39 00 00 40 00 00 02 DF 00
39 00 00 40 00 00 02 6F 36
39 00 00 40 00 00 02 DF 01
];
oplus,dsi-lhbm-pressed-icon-on-pwm-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 16 01 00 87 00 00 25
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 30
39 00 00 40 00 00 02 DF 00
39 00 00 40 00 00 02 6F 36
39 00 00 40 00 00 02 DF 01
];
oplus,dsi-timing-switch-command-state = "dsi_hs_mode";
oplus,dsi-on-command-state = "dsi_lp_mode";
@ -157,6 +183,8 @@ timing@sa_fhd_120 {
oplus,dsi-panel-aod-off-insert-black-command-state = "dsi_ls_mode";
oplus,dsi-hbm-on-command-state = "dsi_hs_mode";
oplus,dsi-hbm-off-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-pwm-command-state = "dsi_hs_mode";
oplus,dsc-params-entries = <&dsc_params>;
//oplus,spr-params-entries = <&spr_params>;
oplus,phy-timcon {
@ -338,6 +366,32 @@ timing@sa_fhd_60 {
oplus,dsi-hbm-off-command = [
39 00 00 00 00 00 03 51 0D BB
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 06 01 00 87 00 00 05
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 30
39 00 00 40 00 00 02 DF 02
39 00 00 40 00 00 02 6F 36
39 00 00 40 00 00 02 DF 03
];
oplus,dsi-lhbm-pressed-icon-on-pwm-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 16 01 00 87 00 00 25
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 6F 30
39 00 00 40 00 00 02 DF 02
39 00 00 40 00 00 02 6F 36
39 00 00 40 00 00 02 DF 03
];
oplus,dsi-timing-switch-command-state = "dsi_hs_mode";
oplus,dsi-on-command-state = "dsi_lp_mode";
@ -345,6 +399,8 @@ timing@sa_fhd_60 {
oplus,dsi-panel-aod-off-insert-black-command-state = "dsi_ls_mode";
oplus,dsi-hbm-on-command-state = "dsi_hs_mode";
oplus,dsi-hbm-off-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-pwm-command-state = "dsi_hs_mode";
oplus,dsc-params-entries = <&dsc_params>;
//oplus,spr-params-entries = <&spr_params>;
oplus,phy-timcon {
@ -368,7 +424,7 @@ display-mode@0 {
fhd-vfp = <52>;
fhd-vsa = <14>;
fhd-vbp = <22>;
hskew = <STANDARD_ADFR>;
hskew = <STANDARD_MFR>;
};
display-mode@1 {
hdisplay = <1080>;
@ -379,7 +435,7 @@ display-mode@1 {
fhd-vfp = <52>;
fhd-vsa = <14>;
fhd-vbp = <22>;
hskew = <STANDARD_ADFR>;
hskew = <STANDARD_MFR>;
};
};
};
@ -528,6 +584,22 @@ timing@sa_fhd_90 {
oplus,dsi-hbm-off-command = [
39 00 00 00 00 00 03 51 0D BB
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 06 01 00 87 00 00 05
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
];
oplus,dsi-lhbm-pressed-icon-on-pwm-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 16 01 00 87 00 00 25
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
];
oplus,dsi-timing-switch-command-state = "dsi_hs_mode";
oplus,dsi-on-command-state = "dsi_lp_mode";
@ -535,6 +607,8 @@ timing@sa_fhd_90 {
oplus,dsi-panel-aod-off-insert-black-command-state = "dsi_ls_mode";
oplus,dsi-hbm-on-command-state = "dsi_hs_mode";
oplus,dsi-hbm-off-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-pwm-command-state = "dsi_hs_mode";
oplus,dsc-params-entries = <&dsc_params>;
//oplus,spr-params-entries = <&spr_params>;
oplus,phy-timcon {
@ -695,17 +769,45 @@ timing@sa_fhd_144 {
15 00 00 40 00 00 02 38 00
39 00 00 00 00 00 03 51 00 00
];
oplus,dsi-panel-aod-off-insert-black-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 00
39 00 00 40 00 00 02 C0 70
39 00 00 40 00 00 06 F0 55 AA 52 08 01
39 00 00 40 00 00 02 6F 01
39 00 00 40 00 00 02 D2 11
39 00 00 40 00 00 02 38 00
39 00 00 00 00 00 03 51 00 00
];
oplus,dsi-hbm-on-command = [
39 00 00 00 00 00 03 51 0F FF
];
oplus,dsi-hbm-off-command = [
39 00 00 00 00 00 03 51 0D BB
];
oplus,dsi-lhbm-pressed-icon-on-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 06 01 00 87 00 00 05
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
];
oplus,dsi-lhbm-pressed-icon-on-pwm-command = [
39 00 00 40 00 00 06 F0 55 AA 52 08 08
39 00 00 40 00 00 02 6F 4A
39 00 00 40 00 00 0D A9 02 00 DF 31 31 16 01 00 87 00 00 25
39 00 00 40 00 00 06 F0 55 AA 52 08 04
39 00 00 40 00 00 02 CB 37
39 00 00 00 00 00 02 8B 10
];
oplus,dsi-timing-switch-command-state = "dsi_hs_mode";
oplus,dsi-on-command-state = "dsi_lp_mode";
oplus,dsi-aod-off-command-state = "dsi_ls_mode";
oplus,dsi-panel-aod-off-insert-black-command-state = "dsi_ls_mode";
oplus,dsi-hbm-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-command-state = "dsi_hs_mode";
oplus,dsi-lhbm-pressed-icon-on-pwm-command-state = "dsi_hs_mode";
oplus,dsi-hbm-off-command-state = "dsi_hs_mode";
oplus,dsc-params-entries = <&dsc_params>;
//oplus,spr-params-entries = <&spr_params>;
@ -772,7 +874,7 @@ oplus,dsi-display-panel@0 {
oplus,backlight-check-disable;
oplus,demura-dbv-enable;
//oplus,emduty-dbv-cfg = <699 772 843 900 929 1153>;
oplus,demura-dbv-cfg = <1153 4094>;
oplus,demura-dbv-cfg = <1153>;
/* PWM config */
oplus,pwm-turbo-support = <0>; /* 0 not support, 1 with switch, 2 Global high frequency pwm without switch */
oplus,pwm-switch-backlight-threshold = <0x481>;
@ -783,6 +885,7 @@ oplus,dsi-display-panel@0 {
oplus,ofp-fp-local-hbm-calibration;
oplus,ofp-longrui-aod-config = <0x02>;
oplus,ofp-need-aod-off-insert-black-frame;
oplus,ofp-no-need-a-mirror-to-the-end;
/* ext_params */
oplus,panel-type = <2>;
oplus,keep_ulps = <1>;

5
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus_chg/oplus_charge_24813.dtsi
View File

@ -576,7 +576,7 @@ oplus_chg_comm: oplus,comm {
oplus_spec,vbatt-ov-thr-mv = <4600>;
oplus_spec,full_pre_ffc_judge;
oplus_spec,full-pre-ffc-mv = <4495>;
oplus_spec,full-pre-ffc-mv = <4530>;
oplus_spec,ffc-temp-thr = <120 210 350 440>;
oplus_spec,wired-ffc-step-max = <2>;
oplus_spec,wired-ffc-fv-mv = <4630 4630>;
@ -756,7 +756,6 @@ oplus_ufcs_charge: oplus,ufcs_charge {
oplus,cp_ic = <&oplus_virtual_cp>;
oplus,dpdm_switch_ic = <&oplus_virtual_dpdm_switch>;
oplus,ufcs_boot_time_retry = <10>;
oplus,impedance_unit = <&oplus_ufcs_impedance_unit>;
oplus,ufcs_need_reset_adapter;
@ -1386,7 +1385,7 @@ strategy_soc_range_high {
11000 4330 1000 0 0
11000 4560 900 0 0
11000 4570 500 1 0>;
strategy_temp_little_cool = <11000 4650 1500 0 0
strategy_temp_little_cool = <11000 4560 1500 0 0
11000 4560 1000 0 0
11000 4570 600 1 0>;
strategy_temp_little_cool_high = <11000 4560 1500 0 0

12
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus_chg/oplus_chg.h
View File

@ -271,6 +271,7 @@
#define OPLUS_IC_FUNC_GAUGE_GET_DEC_CV_SOH (OPLUS_IC_FUNC_NUM_GAUGE_START + 94)
#define OPLUS_IC_FUNC_GAUGE_SET_VCT (OPLUS_IC_FUNC_NUM_GAUGE_START + 95)
#define OPLUS_IC_FUNC_GAUGE_GET_VCT (OPLUS_IC_FUNC_NUM_GAUGE_START + 96)
/* misc */
#define OPLUS_IC_FUNC_NUM_MISC_START 500
#define OPLUS_IC_FUNC_GET_CHARGER_CYCLE (OPLUS_IC_FUNC_NUM_MISC_START + 0)
@ -351,6 +352,17 @@
#define OPLUS_IC_FUNC_GAUGE_SET_RESET_GAUGE_DATE (OPLUS_IC_FUNC_NUM_GAUGE2_START + 2)
#define OPLUS_IC_FUNC_GAUGE_GET_BATT_IC_SN (OPLUS_IC_FUNC_NUM_GAUGE2_START + 3)
/* gauge sec */
#define OPLUS_IC_FUNC_NUM_GAUGE_SEC_START 1300
#define OPLUS_IC_FUNC_GAUGE_SEC_GET_ROMID (OPLUS_IC_FUNC_NUM_GAUGE_SEC_START + 0)
#define OPLUS_IC_FUNC_GAUGE_SEC_WRITE_PAGE (OPLUS_IC_FUNC_NUM_GAUGE_SEC_START + 1)
#define OPLUS_IC_FUNC_GAUGE_SEC_READ_PAGE (OPLUS_IC_FUNC_NUM_GAUGE_SEC_START + 2)
#define OPLUS_IC_FUNC_GAUGE_SEC_ECDSA (OPLUS_IC_FUNC_NUM_GAUGE_SEC_START + 3)
#define OPLUS_IC_FUNC_GAUGE_SEC_ECW (OPLUS_IC_FUNC_NUM_GAUGE_SEC_START + 4)
#define OPLUS_IC_FUNC_GAUGE_SEC_SHUTDOWN (OPLUS_IC_FUNC_NUM_GAUGE_SEC_START + 5)
#define OPLUS_IC_FUNC_GAUGE_SEC_SET_PRIKEY (OPLUS_IC_FUNC_NUM_GAUGE_SEC_START + 6)
#define OPLUS_IC_FUNC_GAUGE_SEC_GET_PRIKEY_INDEX (OPLUS_IC_FUNC_NUM_GAUGE_SEC_START + 7)
#define VOOC_VERSION_DEFAULT 0x0
#define VOOC_VERSION_1_0 0x1
#define VOOC_VERSION_2_0 0x2

4
kernel/kernel_device_modules-6.6/arch/arm64/boot/dts/mediatek/oplus_misc_24813.dtsi
View File

@ -23,6 +23,10 @@ &u2port0 {
mediatek,eye-term-host = <7>;
mediatek,rev6-host = <3>;
mediatek,discth = <0xb>;
mediatek,rx-sqth = <0x2>;
mediatek,rx-sqd = <0x2>;
mediatek,host-rx-sqth = <0xc>;
mediatek,host-rx-sqd = <0x3>;
};
&i2c5 {

3
kernel/kernel_device_modules-6.6/arch/arm64/configs/mgk_64_k66_defconfig
View File

@ -1008,6 +1008,7 @@ CONFIG_OPLUS_FEATURE_SCHED_SPREAD=y
CONFIG_OPLUS_ADD_CORE_CTRL_MASK=y
CONFIG_OPLUS_FEATURE_BAN_APP_SET_AFFINITY=y
CONFIG_OPLUS_CPU_AUDIO_PERF=y
CONFIG_OPLUS_FEATURE_SCHED_DDL=y
CONFIG_OPLUS_FEATURE_LOADBALANCE=y
CONFIG_OPLUS_FEATURE_TASK_CPUSTATS=m
CONFIG_OPLUS_FEATURE_TASK_SCHED=m
@ -1032,4 +1033,4 @@ CONFIG_OPLUS_CAM_EVENT_REPORT=m
#ifdef CONFIG_OPLUS_FEATURE_FREQ_TUNE
CONFIG_OPLUS_FEATURE_FREQ_TUNE=m
#endif
#endif

23
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mediatek_v2/mtk_disp_recovery.c
View File

@ -238,7 +238,8 @@ int _mtk_esd_check_read(struct drm_crtc *crtc)
cmdq_pkt_wfe(cmdq_handle,
mtk_crtc->gce_obj.event[EVENT_CABC_EOF]);
cmdq_pkt_set_event(cmdq_handle,
mtk_crtc->gce_obj.event[EVENT_STREAM_BLOCK]);
/* Record Vblank start timestamp */
mtk_vblank_config_rec_start(mtk_crtc, cmdq_handle, ESD_CHECK);
@ -639,6 +640,8 @@ int mtk_drm_esd_testing_process(struct mtk_drm_esd_ctx *esd_ctx, bool need_lock)
#endif /* OPLUS_FEATURE_DISPLAY_MAINLINE*/
#endif /* OPLUS_FEATURE_DISPLAY */
unsigned int crtc_idx = 0;
struct cmdq_pkt *handle = NULL;
struct mtk_panel_ext *panel_ext;
if (!esd_ctx) {
DDPPR_ERR("%s invalid ESD context, stop thread\n", __func__);
@ -655,6 +658,7 @@ int mtk_drm_esd_testing_process(struct mtk_drm_esd_ctx *esd_ctx, bool need_lock)
}
mtk_crtc = to_mtk_crtc(crtc);
panel_ext = mtk_crtc->panel_ext;
if (!mtk_crtc) {
DDPPR_ERR("%s invalid mtk_crtc stop thread\n", __func__);
return -EINVAL;
@ -670,6 +674,19 @@ int mtk_drm_esd_testing_process(struct mtk_drm_esd_ctx *esd_ctx, bool need_lock)
i = 0; /* repeat */
do {
if (mtk_crtc_is_frame_trigger_mode(esd_ctx->crtc) && esd_ctx->chk_mode == READ_LCM) {
int index = drm_crtc_index(crtc);
if (mtk_drm_is_idle(crtc)) {
DDPINFO("[ESD%u]%s esd check in idle\n", index, __func__);
mtk_drm_idlemgr_kick(__func__, &mtk_crtc->base, index);
}
mtk_crtc_pkt_create(&handle, &mtk_crtc->base,
mtk_crtc->gce_obj.client[CLIENT_CFG]);
cmdq_pkt_clear_event(handle, mtk_crtc->gce_obj.event[EVENT_STREAM_BLOCK]);
cmdq_pkt_flush(handle);
cmdq_pkt_destroy(handle);
}
CRTC_MMP_MARK(crtc_idx, esd_check, 0x00ff, 0);
mtk_drm_trace_begin("esd loop:%d", i);
ret = mtk_drm_esd_check(crtc);
if (!ret && !debug_force_esd) /* success */
@ -938,6 +955,10 @@ void mtk_disp_esd_check_switch(struct drm_crtc *crtc, bool enable)
atomic_set(&esd_ctx->check_wakeup, enable);
if (enable)
wake_up_interruptible(&esd_ctx->check_task_wq);
#ifdef OPLUS_FEATURE_DISPLAY
esd_ctx->esd_check_cnt = 0;
#endif
}
static void mtk_disp_esd_chk_deinit(struct drm_crtc *crtc)

3
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mediatek_v2/mtk_disp_recovery.h
View File

@ -28,6 +28,9 @@ struct mtk_drm_esd_ctx {
u32 chk_sta;
u32 chk_en;
u32 chk_retry;
#ifdef OPLUS_FEATURE_DISPLAY
unsigned int esd_check_cnt;
#endif
};
int mtk_drm_esd_testing_process(struct mtk_drm_esd_ctx *esd_ctx, bool need_lock);

98
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mediatek_v2/mtk_drm_crtc.c
View File

@ -3042,6 +3042,12 @@ int mtk_drm_aod_setbacklight(struct drm_crtc *crtc, unsigned int level)
DDP_MUTEX_UNLOCK(&mtk_crtc->lock, __func__, __LINE__);
return -EINVAL;
}
if (mtk_crtc_with_sub_path(crtc, mtk_crtc->ddp_mode))
mtk_crtc_wait_frame_done(mtk_crtc, cmdq_handle,
DDP_SECOND_PATH, 0);
else
mtk_crtc_wait_frame_done(mtk_crtc, cmdq_handle,
DDP_FIRST_PATH, 0);
if (is_frame_mode) {
cmdq_pkt_clear_event(cmdq_handle,
@ -3050,13 +3056,6 @@ int mtk_drm_aod_setbacklight(struct drm_crtc *crtc, unsigned int level)
mtk_crtc->gce_obj.event[EVENT_CABC_EOF]);
}
if (mtk_crtc_with_sub_path(crtc, mtk_crtc->ddp_mode))
mtk_crtc_wait_frame_done(mtk_crtc, cmdq_handle,
DDP_SECOND_PATH, 0);
else
mtk_crtc_wait_frame_done(mtk_crtc, cmdq_handle,
DDP_FIRST_PATH, 0);
/* Record Vblank start timestamp */
mtk_vblank_config_rec_start(mtk_crtc, cmdq_handle, SET_BL);
@ -5470,7 +5469,6 @@ bool mtk_crtc_alloc_sram(struct mtk_drm_crtc *mtk_crtc, unsigned int hrt_idx)
DDPMSG("%s slbc callback registered\n", __func__);
}
mutex_lock(&mtk_crtc->mml_ir_sram.ref_lock);
mutex_lock(&mtk_crtc->mml_ir_sram.lock);
if (kref_read(&mtk_crtc->mml_ir_sram.ref) < 1) {
@ -5492,14 +5490,7 @@ bool mtk_crtc_alloc_sram(struct mtk_drm_crtc *mtk_crtc, unsigned int hrt_idx)
kref_init(&mtk_crtc->mml_ir_sram.ref);
} else {
if (kref_read(&mtk_crtc->mml_ir_sram.ref) < 0 ||
kref_read(&mtk_crtc->mml_ir_sram.ref) >= INT_MAX)
DDPAEE("%s, mml_ir_sram ref (%d) will saturate\n",
__func__, kref_read(&mtk_crtc->mml_ir_sram.ref));
ret = kref_get_unless_zero(&mtk_crtc->mml_ir_sram.ref);
if (!ret)
DDPAEE("%s, mml_ir_sram ref (%d) zero\n",
__func__, kref_read(&mtk_crtc->mml_ir_sram.ref));
kref_get(&mtk_crtc->mml_ir_sram.ref);
}
mtk_crtc->mml_ir_sram.expiry_hrt_idx = hrt_idx;
@ -5507,7 +5498,6 @@ bool mtk_crtc_alloc_sram(struct mtk_drm_crtc *mtk_crtc, unsigned int hrt_idx)
done:
mutex_unlock(&mtk_crtc->mml_ir_sram.lock);
mutex_unlock(&mtk_crtc->mml_ir_sram.ref_lock);
return (ret == 0 ? true : false);
}
@ -5520,10 +5510,8 @@ static void mtk_crtc_free_sram(struct mtk_drm_crtc *mtk_crtc)
DDPMSG("%s address:0x%lx size:0x%lx\n", __func__,
(unsigned long)mtk_crtc->mml_ir_sram.data.paddr, mtk_crtc->mml_ir_sram.data.size);
mutex_lock(&mtk_crtc->mml_ir_sram.lock);
slbc_power_off(&mtk_crtc->mml_ir_sram.data);
slbc_release(&mtk_crtc->mml_ir_sram.data);
mutex_unlock(&mtk_crtc->mml_ir_sram.lock);
DRM_MMP_MARK(sram_free, (unsigned long)mtk_crtc->mml_ir_sram.data.paddr,
mtk_crtc->mml_ir_sram.expiry_hrt_idx);
@ -10247,11 +10235,11 @@ static void ddp_cmdq_cb(struct cmdq_cb_data data)
drm_writeback_signal_completion(&mtk_crtc->wb_connector, 0);
}
mutex_lock(&mtk_crtc->mml_ir_sram.ref_lock);
mutex_lock(&mtk_crtc->mml_ir_sram.lock);
if (kref_read(&mtk_crtc->mml_ir_sram.ref) &&
(cb_data->hrt_idx > mtk_crtc->mml_ir_sram.expiry_hrt_idx))
kref_put(&mtk_crtc->mml_ir_sram.ref, mtk_crtc_mml_clean);
mutex_unlock(&mtk_crtc->mml_ir_sram.ref_lock);
mutex_unlock(&mtk_crtc->mml_ir_sram.lock);
{ /* OVL reset debug */
unsigned int i;
@ -13700,6 +13688,7 @@ void mtk_crtc_stop(struct mtk_drm_crtc *mtk_crtc, bool need_wait)
mtk_disp_clear_channel_srt_bw(mtk_crtc);
/* 3.1 stop the last mml pkt */
mutex_lock(&mtk_crtc->mml_ir_sram.lock);
if (kref_read(&mtk_crtc->mml_ir_sram.ref)) {
if (mtk_crtc_is_frame_trigger_mode(crtc) || mtk_crtc_is_connector_enable(mtk_crtc))
mtk_crtc_mml_racing_stop_sync(crtc, cmdq_handle, false);
@ -13707,6 +13696,7 @@ void mtk_crtc_stop(struct mtk_drm_crtc *mtk_crtc, bool need_wait)
mtk_crtc_free_sram(mtk_crtc);
refcount_set(&mtk_crtc->mml_ir_sram.ref.refcount, 0);
}
mutex_unlock(&mtk_crtc->mml_ir_sram.lock);
if ((crtc_id == 0) && priv && priv->mml_ctx)
mml_drm_kick_done(priv->mml_ctx);
@ -18216,67 +18206,28 @@ static void mtk_drm_wb_cb(struct cmdq_cb_data data)
struct mtk_cmdq_cb_data *cb_data = data.data;
struct drm_crtc *crtc = cb_data->crtc;
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_crtc_state *state;
struct mtk_drm_private *priv = NULL;
int session_id;
unsigned int i;
int sec_on = 0;
unsigned int fence_idx = cb_data->wb_fence_idx;
struct pixel_type_map *pixel_types;
unsigned int spr_mode_type,bw_zero;
unsigned int spr_mode_type;
if (mtk_crtc->base.dev && mtk_crtc->base.dev->dev_private)
priv = mtk_crtc->base.dev->dev_private;
if (mtk_crtc->pq_data) {
spr_mode_type = mtk_get_cur_spr_type(crtc);
pixel_types = &mtk_crtc->pq_data->pixel_types;
pixel_types->map[pixel_types->head].fence_idx = fence_idx;
pixel_types->map[pixel_types->head].type = spr_mode_type;
pixel_types->map[pixel_types->head].secure = false;
DDPDBG("%s: idx %d fence %u type %u", __func__,
pixel_types->head, fence_idx, spr_mode_type);
pixel_types->head += 1;
pixel_types->head %= SPR_TYPE_FENCE_MAX;
}
if (mtk_crtc->pq_data) {
spr_mode_type = mtk_get_cur_spr_type(crtc);
pixel_types = &mtk_crtc->pq_data->pixel_types;
pixel_types->map[pixel_types->head].fence_idx = fence_idx;
pixel_types->map[pixel_types->head].type = spr_mode_type;
pixel_types->map[pixel_types->head].secure = false;
DDPDBG("%s: idx %d fence %u type %u", __func__,
pixel_types->head, fence_idx, spr_mode_type);
pixel_types->head += 1;
pixel_types->head %= SPR_TYPE_FENCE_MAX;
}
/* fb reference conut will also have 1 after put */
// drm_framebuffer_put(cb_data->wb_fb);
// drm_framebuffer_put(cb_data->wb_fb);
session_id = mtk_get_session_id(crtc);
mtk_crtc_release_output_buffer_fence_by_idx(crtc, session_id, fence_idx);
DDPINFO("%s: fence %u\n", __func__, fence_idx);
// reset wb sec_on state to enter idle
DDP_MUTEX_LOCK(&mtk_crtc->lock, __func__, __LINE__);
for (i = 0; i < mtk_crtc->layer_nr; i++) {
struct drm_plane *plane = &mtk_crtc->planes[i].base;
if (plane->state->crtc) {
if (plane->state->fb
&& plane->state->fb->format->format
!= DRM_FORMAT_C8
&& mtk_drm_fb_is_secure(plane->state->fb))
sec_on = true;
}
}
mtk_crtc->sec_on = sec_on;
if (crtc->state) {
state = to_mtk_crtc_state(crtc->state);
if(fence_idx >= state->prop_val[CRTC_PROP_OUTPUT_FENCE_IDX])
state->prop_val[CRTC_PROP_OUTPUT_ENABLE] = 0;
}
DDP_MUTEX_UNLOCK(&mtk_crtc->lock, __func__, __LINE__);
bw_zero = 0;
if (priv && priv->power_state) {
DDP_MUTEX_LOCK(&mtk_crtc->lock, __func__, __LINE__);
mtk_addon_path_io_cmd(crtc, cb_data->wb_scn, PMQOS_SET_HRT_BW, &bw_zero);
DDP_MUTEX_UNLOCK(&mtk_crtc->lock, __func__, __LINE__);
}
CRTC_MMP_MARK(0, wbBmpDump, 1, fence_idx);
mtk_dprec_mmp_dump_wdma_layer(crtc, cb_data->wb_fb);
@ -21474,7 +21425,6 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
mutex_init(&mtk_crtc->lock);
mutex_init(&mtk_crtc->sol_lock);
mutex_init(&mtk_crtc->cwb_lock);
mutex_init(&mtk_crtc->mml_ir_sram.ref_lock);
mutex_init(&mtk_crtc->mml_ir_sram.lock);
spin_lock_init(&mtk_crtc->pf_time_lock);
mtk_crtc->config_regs = priv->config_regs;

1
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mediatek_v2/mtk_drm_crtc.h
View File

@ -1009,7 +1009,6 @@ struct mtk_drm_sram_list {
struct mtk_drm_sram {
struct slbc_data data;
struct mutex lock;
struct mutex ref_lock;
struct kref ref;
unsigned int expiry_hrt_idx;
};

28
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mediatek_v2/mtk_drm_drv.c
View File

@ -9475,33 +9475,6 @@ void mtk_drm_wait_mml_submit_done(struct mtk_mml_cb_para *cb_para)
DDPINFO("%s- ret:%d\n", __func__, ret);
}
static void mtk_drm_mmlsys_dump_cb(void *cb_param)
{
struct drm_crtc *crtc = (struct drm_crtc *)cb_param;
struct mtk_drm_crtc *mtk_crtc;
struct cmdq_client *cl;
dma_addr_t trig_pc = 0;
u64 *inst;
mtk_crtc = to_mtk_crtc(crtc);
mtk_drm_crtc_analysis(crtc);
mtk_drm_crtc_dump(crtc);
if ((mtk_crtc->trig_loop_cmdq_handle) &&
(mtk_crtc->trig_loop_cmdq_handle->cl)) {
cl = (struct cmdq_client *)mtk_crtc->trig_loop_cmdq_handle->cl;
DDPMSG("++++++ Dump trigger loop ++++++\n");
cmdq_thread_dump(cl->chan, mtk_crtc->trig_loop_cmdq_handle,
&inst, &trig_pc);
cmdq_dump_pkt(mtk_crtc->trig_loop_cmdq_handle, trig_pc, true);
DDPMSG("------ Dump trigger loop ------\n");
}
}
struct mml_drm_ctx *mtk_drm_get_mml_drm_ctx(struct drm_device *dev,
struct drm_crtc *crtc)
{
@ -9538,7 +9511,6 @@ struct mml_drm_ctx *mtk_drm_get_mml_drm_ctx(struct drm_device *dev,
disp_param.ddren_cb = mtk_drm_mmlsys_ddren_cb;
disp_param.kick_idle_cb = mtk_drm_mmlsys_kick_idle_cb;
disp_param.disp_crtc = (void *)crtc;
disp_param.disp_dump_dl_cb = mtk_drm_mmlsys_dump_cb;
mml_ctx = mml_drm_get_context(mml_pdev, &disp_param);
if (IS_ERR_OR_NULL(mml_ctx)) {

134
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mediatek_v2/mtk_dsi.c
View File

@ -67,6 +67,9 @@
#include "oplus_display_onscreenfingerprint.h"
#endif /* OPLUS_FEATURE_DISPLAY_ONSCREENFINGERPRINT */
#ifdef OPLUS_FEATURE_DISPLAY
#include <soc/oplus/system/oplus_project.h>
#endif
/* ************ Panel Master ********** */
#include "mtk_fbconfig_kdebug.h"
/* ********* end Panel Master *********** */
@ -501,6 +504,7 @@ extern unsigned int oplus_display_brightness;
extern atomic_t oplus_pcp_handle_lock;
extern unsigned int oplus_display_log_type;
extern unsigned long oplus_esd_triggered;
extern unsigned int get_project(void);
#endif /* OPLUS_FEATURE_DISPLAY */
#ifdef OPLUS_FEATURE_DISPLAY_APOLLO
@ -4352,7 +4356,11 @@ irqreturn_t mtk_dsi_irq_status(int irq, void *dev_id)
mtk_dump_comp_str(comp));
#ifdef OPLUS_FEATURE_DISPLAY
DDPAEE("buffer underrun. triger kernel_api db\n");
if (get_eng_version() == 0x00) {
DDPAEE_FATAL("buffer underrun. (release) triger kernel_api db isu \n");
} else {
DDPAEE("buffer underrun. triger kernel_api db all log\n");
}
#endif /* OPLUS_FEATURE_DISPLAY */
mtk_vidle_force_power_ctrl_by_cpu(true);
@ -7543,14 +7551,39 @@ int mtk_dsi_esd_read(struct mtk_ddp_comp *comp, void *handle, void *ptr)
struct mtk_panel_params *params;
struct mipi_dsi_msg read_msg;
unsigned char tx_buf[10];
int prj_id = get_project();
//uintptr_t slot = (uintptr_t)ptr;
#ifdef OPLUS_FEATURE_DISPLAY
unsigned int esd_check_total;
unsigned int esd_check_cnt;
#endif
if (dsi->ext && dsi->ext->params)
params = dsi->ext->params;
else /* can't find panel ext information, stop esd read */
return 0;
for (i = 0 ; i < ESD_CHECK_NUM ; i++) {
#ifdef OPLUS_FEATURE_DISPLAY
esd_check_total = ESD_CHECK_NUM;
esd_check_cnt = dsi->esd_ctx->esd_check_cnt;
if (params->esd_check_repeatedly_cnt) {
esd_check_total = esd_check_cnt + 1;
}
for (i = esd_check_cnt; i < esd_check_total; i++)
#else
for (i = 0; i < ESD_CHECK_NUM; i++)
#endif
{
if (params->lcm_esd_check_table[i].cmd == 0)
break;
#ifdef OPLUS_FEATURE_DISPLAY
if (dsi->ext->funcs && dsi->ext->funcs->esd_check_multipage_pre) {
dsi->ext->funcs->esd_check_multipage_pre(dsi, mipi_dsi_dcs_write_gce2, handle, i);
}
#endif
if (params->lcm_esd_check_table[i].cmd == 0)
break;
@ -7564,17 +7597,31 @@ int mtk_dsi_esd_read(struct mtk_ddp_comp *comp, void *handle, void *ptr)
read_msg.rx_len = params->lcm_esd_check_table[i].count;
_mtk_dsi_read_ddic_by6382(dsi, handle, &read_msg, i, ptr);
} else {
t0.CONFG = 0x00;
t0.Data_ID = 0x37;
t0.Data0 = params->lcm_esd_check_table[i].count;
t0.Data1 = 0;
if ((prj_id == 24069) || (prj_id == 24297)) {
t0.CONFG = 0x00 | HSTX;
t0.Data_ID = 0x37;
t0.Data0 = params->lcm_esd_check_table[i].count;
t0.Data1 = 0;
t1.CONFG = 0x04;
t1.Data0 = params->lcm_esd_check_table[i].cmd;
t1.Data_ID = (t1.Data0 < 0xB0)
? DSI_DCS_READ_PACKET_ID
: DSI_GERNERIC_READ_LONG_PACKET_ID;
t1.Data1 = 0;
t1.CONFG = 0x04 | HSTX;
t1.Data0 = params->lcm_esd_check_table[i].cmd;
t1.Data_ID = (t1.Data0 < 0xB0)
? DSI_DCS_READ_PACKET_ID
: DSI_GERNERIC_READ_LONG_PACKET_ID;
t1.Data1 = 0;
} else {
t0.CONFG = 0x00;
t0.Data_ID = 0x37;
t0.Data0 = params->lcm_esd_check_table[i].count;
t0.Data1 = 0;
t1.CONFG = 0x04;
t1.Data0 = params->lcm_esd_check_table[i].cmd;
t1.Data_ID = (t1.Data0 < 0xB0)
? DSI_DCS_READ_PACKET_ID
: DSI_GERNERIC_READ_LONG_PACKET_ID;
t1.Data1 = 0;
}
mtk_dsi_read_gce(comp, handle, &t0, &t1, i, ptr);
}
@ -7591,6 +7638,10 @@ int mtk_dsi_esd_cmp(struct mtk_ddp_comp *comp, void *handle, void *ptr)
struct esd_check_item *lcm_esd_tb;
struct mtk_panel_params *params;
struct mtk_drm_crtc *mtk_crtc = (struct mtk_drm_crtc *)ptr;
#ifdef OPLUS_FEATURE_DISPLAY
unsigned int esd_check_total;
unsigned int esd_check_cnt;
#endif
if (!dsi->driver_data) {
pr_info("%s: error! dsi->driver_data=NULL! return!\n", __func__);
@ -7602,7 +7653,23 @@ int mtk_dsi_esd_cmp(struct mtk_ddp_comp *comp, void *handle, void *ptr)
else /* can't find panel ext information, stop esd read */
return 0;
for (i = 0; i < ESD_CHECK_NUM; i++) {
#ifdef OPLUS_FEATURE_DISPLAY
esd_check_total = ESD_CHECK_NUM;
esd_check_cnt = dsi->esd_ctx->esd_check_cnt;
if (params->esd_check_repeatedly_cnt) {
esd_check_total = ++dsi->esd_ctx->esd_check_cnt;
if (dsi->esd_ctx->esd_check_cnt == params->esd_check_repeatedly_cnt) {
dsi->esd_ctx->esd_check_cnt = 0;
DDPINFO("%s, esd check done, reset esd_check_cnt\n", __func__);
}
}
for (i = esd_check_cnt; i < esd_check_total; i++)
#else
for (i = 0; i < ESD_CHECK_NUM; i++)
#endif
{
if (dsi->ext->params->lcm_esd_check_table[i].cmd == 0)
break;
@ -7749,7 +7816,6 @@ int mtk_dsi_dump(struct mtk_ddp_comp *comp)
pr_info("%s: error! dsi->driver_data=NULL! return!\n", __func__);
return -1;
}
if (DISP_REG_GET_FIELD(MODE_FLD_REG_MODE_CON,
baddr + DSI_MODE_CTRL(dsi->driver_data))) {
/* VDO mode */
@ -7842,6 +7908,7 @@ unsigned int mtk_dsi_mode_change_index(struct mtk_dsi *dsi,
state->prop_val[CRTC_PROP_DISP_MODE_IDX];
/*Msync 2.0*/
struct mtk_drm_private *priv = (mtk_crtc->base).dev->dev_private;
bool doze_enabled_flag = mtk_dsi_doze_state(dsi);
old_mode = &(mtk_crtc->avail_modes[src_mode_idx]);
adjust_mode = &(mtk_crtc->avail_modes[dst_mode_idx]);
@ -7874,7 +7941,7 @@ unsigned int mtk_dsi_mode_change_index(struct mtk_dsi *dsi,
__func__, __LINE__, adjust_panel_params->dyn.switch_en);
}
}
DDPMSG("%s doze_enabled_flag %d\n", __func__, doze_enabled_flag);
if (cur_panel_params && adjust_panel_params &&
!(dsi->mipi_hopping_sta && (cur_panel_params->dyn.switch_en ||
adjust_panel_params->dyn.switch_en))) {
@ -7890,8 +7957,13 @@ unsigned int mtk_dsi_mode_change_index(struct mtk_dsi *dsi,
mode_chg_index |= MODE_DSI_RES;
}
if (drm_mode_vfp(adjust_mode) != drm_mode_vfp(old_mode))
if (drm_mode_vfp(adjust_mode) != drm_mode_vfp(old_mode)) {
mode_chg_index |= MODE_DSI_VFP;
if (doze_enabled_flag && oplus_ofp_video_mode_30hz_aod_accelerate_is_enabled()) {
mode_chg_index |= MODE_DSI_HFP;
DDPMSG("mode_chg_index flag %d\n", mode_chg_index);
}
}
if (drm_mode_hfp(adjust_mode) != drm_mode_hfp(old_mode))
mode_chg_index |= MODE_DSI_HFP;
@ -13445,6 +13517,7 @@ static void mtk_dsi_vdo_timing_change(struct mtk_dsi *dsi,
state->prop_val[CRTC_PROP_DISP_MODE_IDX]);
//1.fps change index
fps_chg_index = mtk_crtc->mode_change_index;
DDPMSG("fps_chg_index %d", fps_chg_index);
mtk_drm_idlemgr_kick(__func__, &(mtk_crtc->base), 0);
@ -13557,7 +13630,8 @@ static void mtk_dsi_vdo_timing_change(struct mtk_dsi *dsi,
handle, DSI_VFP, dsi->vfp);
#ifdef OPLUS_FEATURE_DISPLAY_ONSCREENFINGERPRINT
if (oplus_ofp_is_supported() && oplus_ofp_video_mode_30hz_aod_is_enabled()) {
if (oplus_ofp_is_supported()
&& (oplus_ofp_video_mode_30hz_aod_is_enabled() || oplus_ofp_video_mode_30hz_aod_accelerate_is_enabled())) {
oplus_ofp_video_mode_aod_handle(dsi->encoder.crtc, dsi->ext, dsi->panel, dsi, mtk_dsi_cmdq_pack_gce, handle);
}
#endif /* OPLUS_FEATURE_DISPLAY_ONSCREENFINGERPRINT */
@ -13719,7 +13793,8 @@ static void mtk_dsi_vdo_timing_change(struct mtk_dsi *dsi,
if (dsi && dsi->ext && dsi->ext->params
&& dsi->ext->params->change_fps_by_vfp_send_cmd) {
#ifdef OPLUS_FEATURE_DISPLAY_ONSCREENFINGERPRINT
if (oplus_ofp_is_supported() && oplus_ofp_video_mode_30hz_aod_is_enabled()) {
if (oplus_ofp_is_supported()
&& (oplus_ofp_video_mode_30hz_aod_is_enabled() || oplus_ofp_video_mode_30hz_aod_accelerate_is_enabled())) {
oplus_ofp_video_mode_aod_handle(dsi->encoder.crtc, dsi->ext, dsi->panel, dsi, mtk_dsi_cmdq_pack_gce, handle);
}
#endif /* OPLUS_FEATURE_DISPLAY_ONSCREENFINGERPRINT */
@ -13803,7 +13878,7 @@ static void mtk_dsi_vdo_aod_ctrl(struct mtk_dsi *dsi,
DDPINFO("%s+\n", __func__);
if(!vdo_aod_cfg)
DDPINFO("aod_en:%d, wfe_cmd_eof:%d, need_dsi_trigger:%d \n",
DDPPR_ERR("aod_en:%d, wfe_cmd_eof:%d, need_dsi_trigger:%d \n",
vdo_aod_cfg->aod_en,vdo_aod_cfg->wfe_cmd_eof, vdo_aod_cfg->need_dsi_trigger);
if (!dsi) {
@ -13824,12 +13899,12 @@ static void mtk_dsi_vdo_aod_ctrl(struct mtk_dsi *dsi,
dst_vfp = vdo_aod_param->dst_vfp;
hfp_byte = ALIGN_TO((dst_hfp * dsi_tmp_buf_bpp - 12), 4);
dsi_mode = readl(dsi->regs + DSI_MODE_CTRL(dsi->driver_data));
DDPINFO("%s, dsi_mode=0x%x, porch_change_flag=0x%x, dst_hfp=%d, dst_vfp=%d\n",
__func__, dsi_mode, porch_change_flag, dst_hfp, dst_vfp);
DDPMSG("%s, dsi_mode=0x%x, porch_change_flag=0x%x, dst_hfp=%d, dst_vfp=%d, , hfp_byte = %x\n",
__func__, dsi_mode, porch_change_flag, dst_hfp, dst_vfp, hfp_byte);
cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL);
if (!cb_data) {
DDPINFO("%s:%d, cb data creation failed\n",
DDPPR_ERR("%s:%d, cb data creation failed\n",
__func__, __LINE__);
return;
}
@ -13884,7 +13959,7 @@ static void mtk_dsi_vdo_aod_ctrl(struct mtk_dsi *dsi,
/*1.2 send cmd: send cmd*/
for (i = 0; i < MAX_DYN_CMD_NUM; i++) {
vdo_aod_param_cmd_list = &vdo_aod_param->vdo_aod_cmd_table[i];
DDPINFO("[zxl_test] 111 num =%d, para_list[0] =0x%x\n",
DDPINFO("num =%d, para_list[0] =0x%x\n",
vdo_aod_param_cmd_list->cmd_num, vdo_aod_param_cmd_list->para_list[0]);
if (vdo_aod_param_cmd_list->cmd_num == 0)
break;
@ -13955,7 +14030,7 @@ static void mtk_dsi_vdo_aod_ctrl(struct mtk_dsi *dsi,
/*1.2 send cmd: send cmd*/
for (i = 0; i < MAX_DYN_CMD_NUM; i++) {
vdo_aod_param_cmd_list = &vdo_aod_param->vdo_aod_cmd_table[i];
DDPINFO("[zxl_test] 222 num =%d, para_list[0] =0x%x\n",
DDPINFO("in_dsi_init ture num =%d, para_list[0] =0x%x\n",
vdo_aod_param_cmd_list->cmd_num, vdo_aod_param_cmd_list->para_list[0]);
if (vdo_aod_param_cmd_list->cmd_num == 0)
break;
@ -14072,7 +14147,7 @@ static void mtk_dsi_set_targetline(struct mtk_ddp_comp *comp,
return;
}
val = (hactive * 9) / 10;
val = (hactive * 7) / 10;
val |= TARGET_NL_EN;
DDPINFO("%s -> h:%u, val:0x%x\n", __func__, hactive, val);
@ -15441,6 +15516,7 @@ static int mtk_dsi_io_cmd(struct mtk_ddp_comp *comp, struct cmdq_pkt *handle,
(struct mtk_vdo_aod_cfg *)params;
mtk_dsi_vdo_aod_ctrl(dsi, crtc, vdo_aod_cfg);
oplus_ofp_set_aod_state(false);
}
break;
case DSI_MSYNC_SWITCH_TE_LEVEL:
@ -16914,16 +16990,20 @@ static int mtk_dsi_probe(struct platform_device *pdev)
num_irqs = platform_irq_count(pdev);
if (num_irqs) {
unsigned int cpu_num = 0;
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "failed to request dsi irq resource\n");
ret = -EPROBE_DEFER;
goto error;
}
irq_set_status_flags(irq, IRQ_TYPE_LEVEL_HIGH);
ret = of_property_read_u32(dev->of_node,
"cpu-num", &cpu_num);
if (cpu_num != 0)
ret = irq_force_affinity(irq, cpumask_of(cpu_num));
ret = devm_request_irq(
&pdev->dev, irq, dsi->driver_data->irq_handler,
IRQF_TRIGGER_NONE | IRQF_SHARED, dev_name(&pdev->dev), dsi);

2
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mediatek_v2/mtk_log.h
View File

@ -355,7 +355,7 @@ int mtk_dprec_logger_pr(unsigned int type, char *fmt, ...);
if (r < 0) { \
pr_err("snprintf error\n"); \
} \
aee_kernel_exception_api(__FILE__, __LINE__, \
aee_kernel_fatal_api(__FILE__, __LINE__, \
DB_OPT_DEFAULT | DB_OPT_FTRACE | \
DB_OPT_MMPROFILE_BUFFER, \
str, string, ##args); \

8
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mediatek_v2/mtk_panel_ext.h
View File

@ -17,7 +17,11 @@
#endif
#define RT_MAX_NUM 10
#ifdef OPLUS_FEATURE_DISPLAY
#define ESD_CHECK_NUM 4
#else
#define ESD_CHECK_NUM 3
#endif
#define MAX_TX_CMD_NUM 20
#define MAX_RX_CMD_NUM 20
#define READ_DDIC_SLOT_NUM 6
@ -551,6 +555,8 @@ struct mtk_panel_params {
#ifdef OPLUS_FEATURE_DISPLAY
bool skip_unnecessary_switch;
unsigned int change_fps_by_vfp_send_cmd_need_delay;
unsigned int esd_te_check_gpio;
unsigned int esd_check_repeatedly_cnt;
#endif /* OPLUS_FEATURE_DISPLAY */
struct mtk_ddic_dsi_cmd send_cmd_to_ddic;
unsigned int cust_esd_check;
@ -866,6 +872,8 @@ struct mtk_panel_funcs {
int (*panel_poweroff)(struct drm_panel *panel);
int (*panel_poweron)(struct drm_panel *panel);
int (*panel_reset)(struct drm_panel *panel);
int (*esd_read_gpio)(struct drm_panel *panel);
int (*esd_check_multipage_pre)(void *dsi, dcs_write_gce cb, void *handle, int i);
int (*oplus_set_power)(uint32_t voltage_id, uint32_t voltage_value);
int (*set_seed)(void *dsi_drv, dcs_write_gce_pack cb, void *handle, unsigned int mode);
int (*oplus_update_power_value)(uint32_t voltage_id);

20
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mml/mtk-mml-core.c
View File

@ -35,10 +35,6 @@ int mtk_mml_msg = 1;
EXPORT_SYMBOL(mtk_mml_msg);
module_param(mtk_mml_msg, int, 0644);
int mml_dl_disp_dump = 1;
EXPORT_SYMBOL(mml_dl_disp_dump);
module_param(mml_dl_disp_dump, int, 0644);
/* see mtk-mml-core.c enum mml_hrt_mode for more detail */
int mtk_mml_hrt_mode;
EXPORT_SYMBOL(mtk_mml_hrt_mode);
@ -864,13 +860,6 @@ static void core_comp_dump(struct mml_task *task, u32 pipe, int cnt)
call_dbg_op(comp, dump);
}
if ((cfg->info.mode == MML_MODE_DIRECT_LINK) ||
(cfg->info.mode == MML_MODE_RACING)) {
if (mml_dl_disp_dump)
cfg->task_ops->disp_dump(task);
}
if (cnt >= 0)
mml_dpc_dump();
@ -1214,11 +1203,9 @@ static u32 mml_core_calc_tput_couple(struct mml_task *task, u32 pixel, u32 pipe)
/* workaround, increase mml throughput to avoid underrun */
task_tput = task_tput * 11 / 10;
}
mml_log("%s panel_w %d data.width %d task_tput %d", __func__, cfg->panel_w, dest->data.width, task_tput);
if (cfg->panel_w > dest->data.width) {
if (cfg->panel_w > dest->data.width)
task_tput = (u32)((u64)task_tput * cfg->panel_w / dest->data.width);
mml_log("%s panel_w > width task_tput %d", __func__, task_tput);
}
} else if (info->mode == MML_MODE_DIRECT_LINK) {
/* workaround, increase mml throughput to avoid underrun */
if (cfg->panel_w > dest->data.width)
@ -1419,9 +1406,6 @@ static void mml_core_dvfs_begin(struct mml_task *task, u32 pipe)
mml_msg_qos("task dvfs begin %p pipe %u throughput %u (%u) bandwidth %u pixel %u dpc %u",
task, pipe, throughput, task_pipe_tmp->throughput[dpc],
task_pipe_tmp->bandwidth, max_pixel, dpc);
mml_log("task dvfs begin %p pipe %u throughput %u (%u) bandwidth %u pixel %u dpc %u",
task, pipe, throughput, task_pipe_tmp->throughput[dpc],
task_pipe_tmp->bandwidth, max_pixel, dpc);
done:
mutex_unlock(&tp->qos_mutex);
mml_trace_ex_end();

2
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mml/mtk-mml-core.h
View File

@ -293,8 +293,6 @@ struct mml_task_ops {
void (*kt_setsched)(struct mml_ctx *ctx);
void (*ddren)(struct mml_task *task, struct cmdq_pkt *pkt, bool enable);
void (*dispen)(struct mml_task *task, bool enable);
void (*disp_dump)(struct mml_task *task);
};
struct mml_config_ops {

39
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mml/mtk-mml-driver.c Normal file → Executable file
View File

@ -18,6 +18,7 @@
#include <linux/debugfs.h>
#include <linux/minmax.h>
#include <linux/dma-mapping.h>
#include <uapi/linux/sched/types.h>
#include <mtk-smmu-v3.h>
@ -147,6 +148,7 @@ struct mml_dev {
struct cmdq_base *cmdq_base;
struct cmdq_client *cmdq_clts[MML_MAX_CMDQ_CLTS];
u8 cmdq_clt_cnt;
struct kthread_worker *kt_config;
u32 sw_ver;
atomic_t drm_cnt;
@ -671,6 +673,11 @@ struct mml_m2m_ctx *mml_dev_create_m2m_ctx(struct mml_dev *mml,
return ctx;
}
struct kthread_worker *mml_dev_get_config_worker(struct mml_dev *mml)
{
return mml->kt_config;
}
struct mml_v4l2_dev *mml_get_v4l2_dev(struct mml_dev *mml)
{
return mml->v4l2_dev;
@ -1383,25 +1390,14 @@ void mml_comp_qos_set(struct mml_comp *comp, struct mml_task *task,
struct mml_comp_config *ccfg, u32 throughput, u32 tput_up)
{
struct mml_frame_config *cfg = task->config;
const struct mml_frame_info *info = &cfg->info;
const struct mml_frame_dest *dest = &info->dest[0];
struct mml_dev *mml = cfg->mml;
struct mml_pipe_cache *cache = &cfg->cache[ccfg->pipe];
struct mml_comp_bw *bw = &comp->bw[cfg->dpc];
u32 srt_bw = bw->srt_bw, hrt_bw = bw->hrt_bw;
u32 stash_srt_bw = bw->stash_srt_bw, stash_hrt_bw = bw->stash_hrt_bw;
const u32 srt_bw = bw->srt_bw, hrt_bw = bw->hrt_bw;
const u32 stash_srt_bw = bw->stash_srt_bw, stash_hrt_bw = bw->stash_hrt_bw;
bool hrt = cfg->info.mode == MML_MODE_RACING || cfg->info.mode == MML_MODE_DIRECT_LINK;
bool updated = false;
mml_log("%s srt_bw %d hrt_bw %d", __func__, srt_bw, hrt_bw);
if (cfg->panel_w > dest->data.width) {
srt_bw = (u32)((u64)srt_bw * cfg->panel_w / dest->data.width);
hrt_bw = (u32)((u64)hrt_bw * cfg->panel_w / dest->data.width);
stash_srt_bw = (u32)((u64)stash_srt_bw * cfg->panel_w / dest->data.width);
stash_hrt_bw = (u32)((u64)stash_hrt_bw * cfg->panel_w / dest->data.width);
mml_log("%s panel_w > width srt_bw %d hrt_bw %d", __func__, srt_bw, hrt_bw);
}
/* store for debug log */
task->pipe[ccfg->pipe].bandwidth = max(srt_bw, task->pipe[ccfg->pipe].bandwidth);
if (srt_bw == mml->port_srt_bw[comp->sysid][comp->larb_port] &&
@ -2266,6 +2262,18 @@ static int mml_probe(struct platform_device *pdev)
return -ENOMEM;
platform_set_drvdata(pdev, mml);
mml->kt_config = kthread_create_worker(0, "mml_work0");
if (IS_ERR(mml->kt_config)) {
ret = PTR_ERR(mml->kt_config);
mml_log("%s create thread fail %d", __func__, ret);
goto err_sys_add;
} else {
struct sched_param kt_param = { .sched_priority = MAX_RT_PRIO - 1 };
ret = sched_setscheduler(mml->kt_config->task, SCHED_FIFO, &kt_param);
mml_log("%s thread work0 ret %d", __func__, ret);
}
mml->pdev = pdev;
mutex_init(&mml->sys_state_mutex);
mutex_init(&mml->ctx_mutex);
@ -2434,6 +2442,11 @@ static int mml_remove(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct mml_dev *mml = platform_get_drvdata(pdev);
if (mml->kt_config) {
kthread_destroy_worker(mml->kt_config);
mml->kt_config = NULL;
}
#ifdef MML_DEBUG_PROC
proc_remove(mml->dbg_procfs);
vfree(mml->debug_buffer);

1
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mml/mtk-mml-driver.h
View File

@ -323,6 +323,7 @@ void mml_dev_put_dle_ctx(struct mml_dev *mml,
void (*ctx_release)(struct mml_dle_ctx *ctx));
struct mml_m2m_ctx *mml_dev_create_m2m_ctx(struct mml_dev *mml,
struct mml_m2m_ctx *(*ctx_create)(struct mml_dev *mml));
struct kthread_worker *mml_dev_get_config_worker(struct mml_dev *mml);
struct mml_v4l2_dev *mml_get_v4l2_dev(struct mml_dev *mml);

63
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mml/mtk-mml-drm-adaptor.c
View File

@ -67,8 +67,6 @@ struct mml_drm_ctx {
void (*dispen_cb)(bool enable, void *dispen_param);
void *dispen_param;
struct completion idle;
void (*disp_dump_dl_cb)(void *disp_crtc);
};
static struct mml_drm_ctx *task_ctx_to_drm(struct mml_task *task)
@ -1097,17 +1095,6 @@ static void drm_task_dispen(struct mml_task *task, bool enable)
ctx->dispen_cb(enable, ctx->dispen_param);
}
static void drm_task_disp_dump(struct mml_task *task)
{
struct mml_drm_ctx *ctx = task_ctx_to_drm(task);
if (!ctx->disp_dump_dl_cb)
return;
ctx->disp_dump_dl_cb(ctx->disp_crtc);
}
static const struct mml_task_ops drm_task_ops = {
.queue = task_queue,
.submit_done = task_submit_done,
@ -1117,8 +1104,6 @@ static const struct mml_task_ops drm_task_ops = {
.kt_setsched = ctx_kt_setsched,
.ddren = drm_task_ddren,
.dispen = drm_task_dispen,
.disp_dump = drm_task_disp_dump,
};
static const struct mml_config_ops drm_config_ops = {
@ -1132,43 +1117,44 @@ static struct mml_drm_ctx *drm_ctx_create(struct mml_dev *mml,
{
static const char * const threads[] = {
"mml_drm_done", "mml_destroy",
"mml_work0", "mml_work1",
NULL, "mml_work1",
};
struct mml_drm_ctx *ctx;
struct mml_drm_ctx *dctx;
int ret;
mml_msg("[drm]%s on dev %p", __func__, mml);
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
dctx = kzalloc(sizeof(*dctx), GFP_KERNEL);
if (!dctx)
return ERR_PTR(-ENOMEM);
ret = mml_ctx_init(&ctx->ctx, mml, threads);
dctx->ctx.kt_config[0] = mml_dev_get_config_worker(mml);
ret = mml_ctx_init(&dctx->ctx, mml, threads);
if (ret) {
kfree(ctx);
kfree(dctx);
return ERR_PTR(ret);
}
ctx->ctx.task_ops = &drm_task_ops;
ctx->ctx.cfg_ops = &drm_config_ops;
ctx->ctx.disp_dual = disp->dual;
ctx->ctx.disp_vdo = disp->vdo_mode;
ctx->ctx.submit_cb = disp->submit_cb;
ctx->ddren_cb = disp->ddren_cb;
ctx->disp_crtc = disp->disp_crtc;
ctx->dispen_cb = disp->dispen_cb;
ctx->dispen_param = disp->dispen_param;
ctx->disp_dump_dl_cb = disp->disp_dump_dl_cb;
ctx->panel_width = MML_DEFAULT_PANEL_W;
ctx->panel_height = MML_DEFAULT_PANEL_H;
dctx->ctx.task_ops = &drm_task_ops;
dctx->ctx.cfg_ops = &drm_config_ops;
dctx->ctx.disp_dual = disp->dual;
dctx->ctx.disp_vdo = disp->vdo_mode;
dctx->ctx.submit_cb = disp->submit_cb;
dctx->ddren_cb = disp->ddren_cb;
dctx->disp_crtc = disp->disp_crtc;
dctx->dispen_cb = disp->dispen_cb;
dctx->dispen_param = disp->dispen_param;
dctx->panel_width = MML_DEFAULT_PANEL_W;
dctx->panel_height = MML_DEFAULT_PANEL_H;
#ifndef MML_FPGA
ctx->timeline = mtk_sync_timeline_create("mml_timeline");
dctx->timeline = mtk_sync_timeline_create("mml_timeline");
#endif
if (!ctx->timeline)
if (!dctx->timeline)
mml_err("[drm]fail to create timeline");
else
mml_msg("[drm]timeline for mml %p", ctx->timeline);
mml_msg("[drm]timeline for mml %p", dctx->timeline);
/* return info to display */
disp->racing_height = mml_sram_get_racing_height(mml);
@ -1177,9 +1163,9 @@ static struct mml_drm_ctx *drm_ctx_create(struct mml_dev *mml,
mml_pw_set_kick_cb(mml, disp->kick_idle_cb, disp->disp_crtc);
/* idle complete event to prevent display ignore put context */
init_completion(&ctx->idle);
init_completion(&dctx->idle);
return ctx;
return dctx;
}
struct mml_drm_ctx *mml_drm_get_context(struct platform_device *pdev,
@ -1231,6 +1217,7 @@ static void drm_ctx_release(struct mml_drm_ctx *dctx)
mml_msg("[drm]%s on ctx %p", __func__, ctx);
ctx->kt_config[0] = NULL; /* clear kthread from mml driver */
mml_ctx_deinit(ctx);
for (i = 0; i < ARRAY_SIZE(ctx->tile_cache); i++)
if (ctx->tile_cache[i].tiles)

3
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mml/mtk-mml-drm-adaptor.h
View File

@ -73,9 +73,6 @@ struct mml_drm_param {
/* [out]The height of racing mode for each output tile in pixel. */
u8 racing_height;
/* [in] */
void (*disp_dump_dl_cb)(void *disp_crtc);
};
/*

17
kernel/kernel_device_modules-6.6/drivers/gpu/drm/mediatek/mml/mtk-mml-tp-mt6899.c
View File

@ -954,6 +954,11 @@ static enum mml_mode tp_query_mode_racing(struct mml_dev *mml, struct mml_frame_
{
struct mml_topology_cache *tp;
u32 pixel;
u32 out_w = info->dest[0].data.width;
u32 out_h = info->dest[0].data.height;
mml_log("%s in crop %d %d out %d %d", __func__, info->dest[0].crop.r.width, info->dest[0].crop.r.height,
info->dest[0].data.width, info->dest[0].data.height);
if (unlikely(mml_racing)) {
if (mml_racing == 2)
@ -1060,10 +1065,14 @@ static enum mml_mode tp_query_mode_racing(struct mml_dev *mml, struct mml_frame_
goto decouple;
}
if ((info->dest[0].data.width > info->dest[0].crop.r.width &&
info->dest[0].data.height < info->dest[0].crop.r.height) ||
(info->dest[0].data.width < info->dest[0].crop.r.width &&
info->dest[0].data.height > info->dest[0].crop.r.height)) {
if (info->dest[0].rotate == MML_ROT_90 ||
info->dest[0].rotate == MML_ROT_270)
swap(out_w, out_h);
if ((out_w > info->dest[0].crop.r.width &&
out_h < info->dest[0].crop.r.height) ||
(out_w < info->dest[0].crop.r.width &&
out_h > info->dest[0].crop.r.height)) {
*reason = mml_query_rszratio;
goto decouple;
}

575
kernel/kernel_device_modules-6.6/drivers/leds/fan/oplus_fan.c
View File

@ -32,7 +32,11 @@
#define MAX_LEVEL_DEFAULT 10
#define DEVICE_ID_HONGYING 0
#define DEVICE_ID_TAIDA 1
#define FAN_STATUS_PERIOD_DEFAULT 60000
static int dbg_rpm = -1;
module_param(dbg_rpm, int, 0644);
MODULE_PARM_DESC(dbg_rpm, "oplus debug fan rpm");
#ifdef CONFIG_OPLUS_FAN_MTK
#define FAN_DEFAULT_PWM_NUM 1
#define FAN_DEFAULT_VDD_MIN_VOL 2950000
@ -45,7 +49,8 @@ struct oplus_fan_tach {
int fg_irq_gpio;
atomic_t pulses;
unsigned int rpm;
bool fg_irq_en;
struct mutex irq_lock;
#ifdef CONFIG_OPLUS_FAN_MTK
u32 pwm_num;
int vdd_type;
@ -55,10 +60,17 @@ struct oplus_fan_tach {
#endif
};
struct fan_rpm_offset_config {
int temp;
u32 rpm_offset;
};
struct fan_hw_config {
int max_level;
int duty_config[MAX_LEVEL_DEFAULT];
struct fan_rpm_offset_config *rpm_offset_config;
int pulses_per_revolution;
int rpm_offset_count;
};
struct pwm_setting {
@ -68,6 +80,31 @@ struct pwm_setting {
bool enabled;
};
struct fan_rpm_table {
u32 duty;
u32 rpm;
};
enum fan_status {
FAN_STATUS_NORMAL = 0,
FAN_STATUS_BLOCKED = 1,
FAN_STATUS_DAMAGED = 2,
};
static const char *const fan_state_names[] = {
[FAN_STATUS_NORMAL] = "NORMAL",
[FAN_STATUS_BLOCKED] = "BLOCKED",
[FAN_STATUS_DAMAGED] = "DAMAGED",
};
static const char *fan_status_string(enum fan_status status)
{
if (status < 0 || status >= ARRAY_SIZE(fan_state_names))
return "UNKNOWN";
return fan_state_names[status];
}
struct oplus_fan_chip {
struct device *dev;
struct mutex lock;
@ -82,9 +119,21 @@ struct oplus_fan_chip {
int reg_en_gpio;
bool regulator_enabled;
bool rpm_timer_enabled;
bool force_rpm_timer_enabled;
struct oplus_fan_tach tach;
ktime_t sample_start;
struct timer_list rpm_timer;
struct delayed_work fan_status_work;
struct delayed_work fan_retry_work;
int status_check_period;
bool force_disable_status_work;
enum fan_status status;
struct fan_rpm_table rpm_table[MAX_LEVEL_DEFAULT];
bool rpm_table_initialized;
bool fan_status_checking;
bool fan_state_retrying;
bool state_changed;
struct thermal_zone_device *shell_themal;
#ifdef CONFIG_OPLUS_FAN_MTK
struct pwm_spec_config mtk_pwm_setting;
#endif
@ -94,6 +143,7 @@ static struct fan_hw_config default_hw_config = {
.max_level = MAX_LEVEL_DEFAULT,
.duty_config = {10, 20, 30, 40, 50, 60, 70, 80, 90, 100},
.pulses_per_revolution = DEFAULT_PULSES_PER_REVOLUTION,
.rpm_offset_config = NULL,
};
/* This handler assumes self resetting edge triggered interrupt. */
@ -136,20 +186,242 @@ static void sample_timer(struct timer_list *t)
dev_err(chip->dev, "sample_timer:delta=%u ms, duty=%u, pulses=%d, rpm=%u\n",
delta, chip->pwm_setting.duty, pulses, tach->rpm);
if (dbg_rpm >= 0) {
tach->rpm = dbg_rpm;
dev_err(chip->dev, "dbg_rpm != 0, force rpm=%u\n", tach->rpm);
}
mod_timer(&chip->rpm_timer, jiffies + HZ);
}
static void restart_sample_timer(struct oplus_fan_chip *chip)
static void oplus_fan_fg_irq_config(struct oplus_fan_chip *chip,
bool enabled)
{
if (!chip)
return;
if (!gpio_is_valid(chip->tach.fg_irq_gpio))
return;
mutex_lock(&chip->tach.irq_lock);
if (!chip->tach.fg_irq_en && enabled) {
enable_irq(gpio_to_irq(chip->tach.fg_irq_gpio));
chip->tach.fg_irq_en = true;
} else if (chip->tach.fg_irq_en && !enabled) {
disable_irq_nosync(gpio_to_irq(chip->tach.fg_irq_gpio));
chip->tach.fg_irq_en = false;
}
mutex_unlock(&chip->tach.irq_lock);
}
static void oplus_fan_sample_timer_enable(struct oplus_fan_chip *chip,
bool enabled)
{
int pulses;
if (!chip)
return;
pulses = atomic_read(&chip->tach.pulses);
atomic_sub(pulses, &chip->tach.pulses);
chip->sample_start = ktime_get();
mod_timer(&chip->rpm_timer, jiffies + HZ);
if (chip->fan_status_checking) {
dev_err(chip->dev, "fan_status_work checking, don't allow change sample_timer state\n");
return;
}
if (chip->force_rpm_timer_enabled && !enabled) {
dev_err(chip->dev, "force_rpm_timer_enabled, don't disable sample_timer\n");
return;
}
chip->rpm_timer_enabled = enabled;
dev_err(chip->dev, "sample_timer enable = %d\n", enabled);
if (enabled) {
oplus_fan_fg_irq_config(chip, true);
pulses = atomic_read(&chip->tach.pulses);
atomic_sub(pulses, &chip->tach.pulses);
chip->sample_start = ktime_get();
mod_timer(&chip->rpm_timer, jiffies + HZ);
} else {
oplus_fan_fg_irq_config(chip, false);
}
}
#define DEFAULT_SHELL_TEMP 25
static int oplus_fan_get_shell_temp(struct oplus_fan_chip *chip)
{
int shell_temp;
struct thermal_zone_device *tmp_shell_themal = NULL;
int rc;
if (chip->shell_themal == NULL) {
tmp_shell_themal = thermal_zone_get_zone_by_name("shell_back");
if (IS_ERR(tmp_shell_themal)) {
dev_err(chip->dev, "Can't get shell_back\n");
tmp_shell_themal = NULL;
}
chip->shell_themal = tmp_shell_themal;
}
if (IS_ERR_OR_NULL(chip->shell_themal)) {
shell_temp = DEFAULT_SHELL_TEMP;
} else {
rc = thermal_zone_get_temp(chip->shell_themal, &shell_temp);
if (rc) {
dev_err(chip->dev, "thermal_zone_get_temp get error");
shell_temp = DEFAULT_SHELL_TEMP;
} else {
shell_temp = shell_temp / 100;
}
}
dev_err(chip->dev, "shell_back temp = %d", shell_temp);
return shell_temp;
}
static u32 oplus_fan_get_target_rpm(struct oplus_fan_chip *chip, u32 duty)
{
int i;
for (i = 0; i < MAX_LEVEL_DEFAULT; i++) {
if (duty == chip->rpm_table[i].duty)
return chip->rpm_table[i].rpm;
}
return 0;
}
#define FAN_RPM_OFFSET_DEFAULT 1000
static u32 oplus_fan_get_rpm_offset(struct oplus_fan_chip *chip, int temp)
{
struct fan_hw_config *config = &chip->hw_config[chip->device_id];
int i;
if (config->rpm_offset_count <= 0)
return FAN_RPM_OFFSET_DEFAULT;
for (i = 0; i < config->rpm_offset_count; i++) {
if (temp < config->rpm_offset_config[i].temp)
return config->rpm_offset_config[i].rpm_offset;
}
return FAN_RPM_OFFSET_DEFAULT;
}
static bool oplus_fan_check_duty_support(struct oplus_fan_chip *chip, u32 duty)
{
int i;
if (duty == 0)
return false;
for (i = 0; i < MAX_LEVEL_DEFAULT; i++) {
if (duty == chip->rpm_table[i].duty)
return true;
}
return false;
}
static bool oplus_fan_check_status_work_needed(struct oplus_fan_chip *chip)
{
if (!chip->rpm_table_initialized) {
dev_err(chip->dev, "rpm_table is not initialized\n");
return false;
}
if (chip->force_disable_status_work) {
dev_err(chip->dev, "force disabled\n");
return false;
}
if (!chip->regulator_enabled || !chip->pwm_setting.enabled) {
dev_err(chip->dev, "fan state is disabled\n");
return false;
}
return true;
}
#define DAMAGED_RPM_THRESHOLD 100
static void oplus_fan_status_work(struct work_struct *work)
{
struct oplus_fan_chip *chip = container_of(work, struct oplus_fan_chip,
fan_status_work.work);
char *normal_strs[2] = { "FAN_STATE=NORMAL", NULL };
char *blocked_strs[2] = { "FAN_STATE=BLOCKED", NULL };
char *damaged_strs[2] = { "FAN_STATE=DAMAGED", NULL };
u32 current_duty;
u32 current_rpm;
u32 target_rpm;
u32 rpm_offset;
int shell_temp;
bool check_block_status;
if (!oplus_fan_check_status_work_needed(chip)) {
dev_err(chip->dev, "fan_status_work:don't need check, return\n");
return;
}
current_duty = chip->pwm_setting.duty;
oplus_fan_sample_timer_enable(chip, true);
chip->fan_status_checking = true;
msleep(1200);
chip->fan_status_checking = false;
oplus_fan_sample_timer_enable(chip, false);
if (!chip->regulator_enabled || !chip->pwm_setting.enabled) {
dev_err(chip->dev, "fan_status_work: fan state changed, return\n");
return;
}
if (current_duty != chip->pwm_setting.duty) {
dev_err(chip->dev, "fan_status_work:duty changed, skip this check\n");
goto next_check;
}
current_rpm = chip->tach.rpm;
check_block_status = oplus_fan_check_duty_support(chip, chip->pwm_setting.duty);
if (check_block_status) {
target_rpm = oplus_fan_get_target_rpm(chip, current_duty);
if (target_rpm == 0) {
dev_err(chip->dev, "fan_status_work:target_rpm = 0, return\n");
return;
}
} else {
target_rpm = 0;
dev_err(chip->dev, "duty=%d not support in rpm_table\n", chip->pwm_setting.duty);
}
shell_temp = oplus_fan_get_shell_temp(chip);
rpm_offset = oplus_fan_get_rpm_offset(chip, shell_temp);
dev_err(chip->dev, "fan_status_work: rpm=%u, level=%d, duty=%u target_rpm=%u, rpm_offset=%u\n",
current_rpm, chip->level, current_duty, target_rpm, rpm_offset);
if (check_block_status && current_rpm > target_rpm + rpm_offset) {
chip->status = FAN_STATUS_BLOCKED;
if (kobject_uevent_env(&chip->cdev.dev->kobj, KOBJ_CHANGE, blocked_strs))
dev_err(chip->dev, "Failed to send fan status uevent\n");
else
dev_err(chip->dev, "sent uevent %s\n", blocked_strs[0]);
} else if (current_rpm < DAMAGED_RPM_THRESHOLD) {
chip->status = FAN_STATUS_DAMAGED;
if (kobject_uevent_env(&chip->cdev.dev->kobj, KOBJ_CHANGE, damaged_strs))
dev_err(chip->dev, "Failed to send fan status uevent\n");
else
dev_err(chip->dev, "sent uevent %s\n", damaged_strs[0]);
} else {
chip->status = FAN_STATUS_NORMAL;
if (kobject_uevent_env(&chip->cdev.dev->kobj, KOBJ_CHANGE, normal_strs))
dev_err(chip->dev, "Failed to send fan status uevent\n");
else
dev_err(chip->dev, "sent uevent %s\n", normal_strs[0]);
}
next_check:
schedule_delayed_work(&chip->fan_status_work, msecs_to_jiffies(chip->status_check_period));
}
static int oplus_fan_parse_hw_config(struct oplus_fan_chip *chip)
@ -157,9 +429,11 @@ static int oplus_fan_parse_hw_config(struct oplus_fan_chip *chip)
struct device_node *np = chip->dev->of_node;
struct device_node *temp;
struct fan_hw_config *config;
int buf[64] = {0};
int ret;
int count;
int i = 0;
int j;
count = of_get_child_count(np);
if (count < 1) {
@ -173,6 +447,8 @@ static int oplus_fan_parse_hw_config(struct oplus_fan_chip *chip)
if (!chip->hw_config) {
dev_err(chip->dev, "failed to kcalloc memory\n");
goto parse_err;
} else {
memset(chip->hw_config, 0, count * sizeof(struct fan_hw_config));
}
for_each_child_of_node(np, temp) {
@ -196,6 +472,34 @@ static int oplus_fan_parse_hw_config(struct oplus_fan_chip *chip)
dev_err(chip->dev, "failed to get duty-config count = %d\n", count);
goto parse_err;
}
count = of_property_count_elems_of_size(temp, "rpm-offset-config", sizeof(int));
if (count > 0 && count % 2 == 0) {
ret = of_property_read_u32_array(temp, "rpm-offset-config", (u32 *)buf, count);
if (ret) {
dev_err(chip->dev, "failed to get rpm-offset-config ret = %d\n", ret);
goto parse_err;
}
config->rpm_offset_count = count / 2;
config->rpm_offset_config = devm_kcalloc(chip->dev,
config->rpm_offset_count, sizeof(struct fan_rpm_offset_config), GFP_KERNEL);
if (!config->rpm_offset_config) {
dev_err(chip->dev, "fail to alloc rpm_offset_config memory\n");
goto parse_err;
}
for (j = 0; j < config->rpm_offset_count; j++) {
config->rpm_offset_config[j].temp = buf[j * 2 + 0];
config->rpm_offset_config[j].rpm_offset = buf[j * 2 + 1];
dev_err(chip->dev, "rpm_offset_config[%d]:temp=%d, rpm_offset=%u\n", j,
config->rpm_offset_config[j].temp,
config->rpm_offset_config[j].rpm_offset);
}
} else {
dev_err(chip->dev, "failed to get rpm-offset-config count = %d\n", count);
goto parse_err;
}
dev_err(chip->dev, "parse config[%d] pulses_per_revolution = %d\n", i, config->pulses_per_revolution);
dev_err(chip->dev, "duty_config = %d,%d,%d,%d,%d, %d,%d,%d,%d,%d\n",
config->duty_config[0], config->duty_config[1], config->duty_config[2],
@ -259,6 +563,8 @@ static int oplus_fan_parse_dt(struct oplus_fan_chip *chip)
gpio_to_irq(tach->fg_irq_gpio), ret);
return ret;
}
disable_irq_nosync(gpio_to_irq(tach->fg_irq_gpio));
tach->fg_irq_en = false;
}
dev_err(chip->dev, "tach: fg_irq_gpio=%d\n", tach->fg_irq_gpio);
@ -343,12 +649,13 @@ static int mtk_oplus_fan_pwm_start(struct oplus_fan_chip *chip)
chip->mtk_pwm_setting.PWM_MODE_OLD_REGS.DATA_WIDTH * chip->pwm_setting.duty /
100;
ret = pwm_set_spec_config(&chip->mtk_pwm_setting);
if (ret) {
dev_err(chip->dev, "Fail to pwm_set_spec_config ret = %d\n", ret);
if (chip->pwm_setting.enabled) {
ret = pwm_set_spec_config(&chip->mtk_pwm_setting);
if (ret) {
dev_err(chip->dev, "Fail to pwm_set_spec_config ret = %d\n", ret);
}
}
dev_err(chip->dev, "mtk_oplus_fan_pwm_start set THRESH = %d", chip->mtk_pwm_setting.PWM_MODE_OLD_REGS.THRESH);
dev_err(chip->dev, "mtk_oplus_fan_pwm_start PWM:enabled=%d, duty=%u", chip->pwm_setting.enabled, chip->pwm_setting.duty);
mutex_unlock(&chip->lock);
@ -363,7 +670,7 @@ static int mtk_oplus_fan_pwm_stop(struct oplus_fan_chip *chip)
mt_pwm_disable(chip->mtk_pwm_setting.pwm_no, chip->mtk_pwm_setting.pmic_pad);
dev_err(chip->dev, "mtk_oplus_fan_pwm_stop pwm\n");
dev_err(chip->dev, "mtk_oplus_fan_pwm_stop PWM:enabled=%d\n", chip->pwm_setting.enabled);
return 0;
}
@ -443,16 +750,26 @@ static void oplus_fan_enable(struct oplus_fan_chip *chip, bool enabled)
if (!chip)
return;
chip->state_changed = false;
if (enabled) {
oplus_fan_regulator_set(chip, true);
msleep(100);
chip->pwm_setting.enabled = true;
oplus_fan_set_pwm(chip);
oplus_fan_sample_timer_enable(chip, true);
cancel_delayed_work_sync(&chip->fan_status_work);
if (chip->fan_state_retrying)
schedule_delayed_work(&chip->fan_retry_work, msecs_to_jiffies(200));
else
schedule_delayed_work(&chip->fan_status_work, msecs_to_jiffies(2000));
} else {
chip->pwm_setting.enabled = false;
oplus_fan_set_pwm(chip);
msleep(100);
oplus_fan_regulator_set(chip, false);
oplus_fan_sample_timer_enable(chip, false);
cancel_delayed_work_sync(&chip->fan_status_work);
}
return;
@ -466,22 +783,88 @@ static void mtk_oplus_fan_enable(struct oplus_fan_chip *chip, bool enabled)
if (enabled == chip->pwm_setting.enabled)
return;
chip->state_changed = false;
if (enabled) {
oplus_fan_regulator_set(chip, true);
msleep(100);
chip->pwm_setting.enabled = true;
mtk_oplus_fan_pwm_start(chip);
oplus_fan_sample_timer_enable(chip, true);
cancel_delayed_work_sync(&chip->fan_status_work);
if (chip->fan_state_retrying)
schedule_delayed_work(&chip->fan_retry_work, msecs_to_jiffies(200));
else
schedule_delayed_work(&chip->fan_status_work, msecs_to_jiffies(2000));
} else {
chip->pwm_setting.enabled = false;
mtk_oplus_fan_pwm_stop(chip);
msleep(100);
oplus_fan_regulator_set(chip, false);
oplus_fan_sample_timer_enable(chip, false);
cancel_delayed_work_sync(&chip->fan_status_work);
}
return;
}
#endif
#define DEFAULT_RETRY_COUNT 3
static void oplus_fan_retry_work(struct work_struct *work)
{
struct oplus_fan_chip *chip = container_of(work, struct oplus_fan_chip,
fan_retry_work.work);
int i;
int count = 0;
for (i = 0; i < DEFAULT_RETRY_COUNT; i++) {
if (chip->state_changed) {
dev_err(chip->dev, "fan state_changed\n");
break;
}
if (!chip->regulator_enabled || !chip->pwm_setting.enabled) {
dev_err(chip->dev, "fan state is disabled\n");
break;
}
oplus_fan_sample_timer_enable(chip, true);
chip->fan_status_checking = true;
msleep(1200);
chip->fan_status_checking = false;
oplus_fan_sample_timer_enable(chip, false);
if (!chip->regulator_enabled || !chip->pwm_setting.enabled) {
dev_err(chip->dev, "fan state is disabled\n");
break;
}
if (chip->tach.rpm < DAMAGED_RPM_THRESHOLD) {
count++;
} else {
break;
}
}
chip->fan_state_retrying = false;
if (count == DEFAULT_RETRY_COUNT) {
dev_err(chip->dev, "fan status abnormal, retry fan enable\n");
#ifndef CONFIG_OPLUS_FAN_MTK
oplus_fan_enable(chip, false);
msleep(20);
oplus_fan_enable(chip, true);
#else
mtk_oplus_fan_enable(chip, false);
msleep(20);
mtk_oplus_fan_enable(chip, true);
#endif
} else {
dev_err(chip->dev, "fan status normal\n");
schedule_delayed_work(&chip->fan_status_work, msecs_to_jiffies(2000));
}
}
static int oplus_fan_init(struct oplus_fan_chip *chip)
{
#ifdef CONFIG_OPLUS_FAN_MTK
@ -491,6 +874,7 @@ static int oplus_fan_init(struct oplus_fan_chip *chip)
return -EINVAL;
}
chip->level = 0;
chip->status_check_period = FAN_STATUS_PERIOD_DEFAULT;
chip->pwm_setting.duty = MAX_DUTY;
#ifndef CONFIG_OPLUS_FAN_MTK
chip->pwm_setting.period_ns = chip->pwm_setting.pre_period_ns;
@ -554,6 +938,7 @@ static ssize_t speed_store(struct device *dev, struct device_attribute *attr,
if (speed > MAX_DUTY)
speed = MAX_DUTY;
chip->level = 0;
chip->pwm_setting.duty = speed;
#ifndef CONFIG_OPLUS_FAN_MTK
oplus_fan_set_pwm(chip);
@ -587,7 +972,11 @@ static ssize_t state_store(struct device *dev, struct device_attribute *attr,
rc = kstrtobool(buf, &enabled);
if (rc < 0)
return rc;
dev_err(chip->dev, "state_store = %d\n", enabled);
chip->state_changed = true;
cancel_delayed_work_sync(&chip->fan_retry_work);
chip->fan_state_retrying = enabled;
#ifndef CONFIG_OPLUS_FAN_MTK
oplus_fan_enable(chip, enabled);
#else
@ -620,11 +1009,9 @@ static ssize_t rpm_store(struct device *dev, struct device_attribute *attr,
if (rc < 0)
return rc;
dev_err(chip->dev, "rpm_timer enable = %d\n", enabled);
chip->rpm_timer_enabled = enabled;
if (enabled)
restart_sample_timer(chip);
chip->force_rpm_timer_enabled = enabled;
dev_err(chip->dev, "rpm_store force_rpm_timer_enabled = %d\n", enabled);
oplus_fan_sample_timer_enable(chip, enabled);
return count;
}
@ -720,12 +1107,156 @@ static ssize_t device_id_store(struct device *dev, struct device_attribute *attr
}
static DEVICE_ATTR_RW(device_id);
static ssize_t status_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct led_classdev *fan_cdev = dev_get_drvdata(dev);
struct oplus_fan_chip *chip =
container_of(fan_cdev, struct oplus_fan_chip, cdev);
return scnprintf(buf, PAGE_SIZE, "%s\n", fan_status_string(chip->status));
}
static DEVICE_ATTR_RO(status);
static ssize_t check_period_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct led_classdev *fan_cdev = dev_get_drvdata(dev);
struct oplus_fan_chip *chip =
container_of(fan_cdev, struct oplus_fan_chip, cdev);
return scnprintf(buf, PAGE_SIZE, "%d\n", chip->status_check_period);
}
static ssize_t check_period_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct led_classdev *fan_cdev = dev_get_drvdata(dev);
struct oplus_fan_chip *chip =
container_of(fan_cdev, struct oplus_fan_chip, cdev);
int rc;
u32 val;
rc = kstrtouint(buf, 0, &val);
if (rc < 0)
return rc;
dev_err(chip->dev, "set check_period = %u\n", val);
if (val == 0) {
chip->force_disable_status_work = true;
dev_err(chip->dev, "force disable check status work\n");
} else {
chip->status_check_period = val;
chip->force_disable_status_work = false;
}
return count;
}
static DEVICE_ATTR_RW(check_period);
static ssize_t rpm_table_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct led_classdev *fan_cdev = dev_get_drvdata(dev);
struct oplus_fan_chip *chip =
container_of(fan_cdev, struct oplus_fan_chip, cdev);
int i;
int count = 0;
for (i = 0; i < MAX_LEVEL_DEFAULT; i++) {
count += scnprintf(buf + count, PAGE_SIZE, "%u,%u,",
chip->rpm_table[i].duty, chip->rpm_table[i].rpm);
dev_err(chip->dev, "rpm_table[%d]:%u,%u\n", i,
chip->rpm_table[i].duty, chip->rpm_table[i].rpm);
}
if (count > 0)
buf[count - 1] = '\n';
return count;
}
static ssize_t rpm_table_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct led_classdev *fan_cdev = dev_get_drvdata(dev);
struct oplus_fan_chip *chip =
container_of(fan_cdev, struct oplus_fan_chip, cdev);
char buffer[128] = {0};
u32 data[MAX_LEVEL_DEFAULT * 2] = {0};
char *str = buffer;
int val;
int cnt = 0;
int i;
if (count > sizeof(buffer) - 1) {
dev_err(chip->dev, "rpm_table data length out of range, count=%zu\n", count);
return -EFAULT;
}
memmove(buffer, buf, count);
dev_err(chip->dev, "rpm_table_store:%s\n", buffer);
while (*str != '\0' && *str != '\n') {
if (sscanf(str, "%d", &val) && val != 0) {
data[cnt++] = val;
str = strstr(str, ",");
if (!str)
break;
else
str++;
if (cnt == MAX_LEVEL_DEFAULT * 2)
break;
} else {
dev_err(chip->dev, "invalid rpm_table data, buffer=%s\n", buffer);
return -EFAULT;
}
}
if (cnt % 2) {
dev_err(chip->dev, "invalid rpm_table data count, buffer=%s\n", buffer);
return -EFAULT;
} else {
/* all duty param must be lower than MAX_DUTY */
for (i = 0; i < cnt; i += 2) {
if (data[i] > MAX_DUTY) {
dev_err(chip->dev, "duty param %u is invalid, buffer=%s\n", data[i], buffer);
return -EFAULT;
}
}
/* all rpm param can't be zero */
for (i = 1; i < cnt; i += 2) {
if (data[i] == 0) {
dev_err(chip->dev, "rpm param %u is invalid, buffer=%s\n", data[i], buffer);
return -EFAULT;
}
}
memset(chip->rpm_table, 0 , sizeof(chip->rpm_table));
dev_err(chip->dev, "rpm_table update count = %d\n", cnt);
for (i = 0; i < (cnt / 2); i++) {
chip->rpm_table[i].duty = data[i * 2];
chip->rpm_table[i].rpm = data[i * 2 + 1];
dev_err(chip->dev, "rpm_table[%d]:%u,%u\n", i, data[i * 2], data[i * 2 + 1]);
}
chip->rpm_table_initialized = true;
}
return count;
}
static DEVICE_ATTR_RW(rpm_table);
static struct attribute *oplus_fan_attrs[] = {
&dev_attr_speed.attr,
&dev_attr_state.attr,
&dev_attr_rpm.attr,
&dev_attr_level.attr,
&dev_attr_device_id.attr,
&dev_attr_status.attr,
&dev_attr_check_period.attr,
&dev_attr_rpm_table.attr,
NULL
};
@ -802,6 +1333,7 @@ static int oplus_fan_probe(struct platform_device *pdev)
return -ENOMEM;
mutex_init(&chip->lock);
mutex_init(&chip->tach.irq_lock);
chip->dev = &pdev->dev;
platform_set_drvdata(pdev, chip);
@ -819,21 +1351,18 @@ static int oplus_fan_probe(struct platform_device *pdev)
dev_err(chip->dev, "failed to kzalloc memory\n");
return ret;
}
memcpy(chip->hw_config, &default_hw_config, sizeof(struct fan_hw_config));
memmove(chip->hw_config, &default_hw_config, sizeof(struct fan_hw_config));
}
chip->device_id = DEVICE_ID_HONGYING;
INIT_DELAYED_WORK(&chip->fan_status_work, oplus_fan_status_work);
INIT_DELAYED_WORK(&chip->fan_retry_work, oplus_fan_retry_work);
timer_setup(&chip->rpm_timer, sample_timer, 0);
ret = devm_add_action_or_reset(dev, oplus_fan_cleanup, chip);
if (ret)
return ret;
oplus_fan_cdev_register(chip);
chip->rpm_timer_enabled = true;
chip->sample_start = ktime_get();
mod_timer(&chip->rpm_timer, jiffies + HZ);
oplus_fan_init(chip);
dev_err(chip->dev, "probe complete!\n");

2
kernel/kernel_device_modules-6.6/drivers/misc/mediatek/boot_common/mtk_boot_common.c
View File

@ -321,7 +321,7 @@ static int boot_mode_proc_show(struct seq_file *p, void *v)
#if 0
#ifdef OPLUS_BUG_STABILITY
OPPO_BOOTMODE oplus_boot_mode = OPLUS_NORMAL_BOOT;
OPLUS_BOOTMODE oplus_boot_mode = OPLUS_NORMAL_BOOT;
static int oplus_get_boot_mode(char *oplus_boot_mode_char)
{
int boot_mode_temp = 0;

68
kernel/kernel_device_modules-6.6/drivers/misc/mediatek/jpeg/jpeg_drv.c
View File

@ -628,41 +628,47 @@ static void jpeg_drv_hybrid_dec_unlock(unsigned int hwid)
mutex_unlock(&jpeg_hybrid_dec_lock);
}
static int jpeg_drv_hybrid_dec_suspend_notifier(
static int jpeg_drv_hybrid_dec_suspend_prepare_notifier(
struct notifier_block *nb,
unsigned long action, void *data)
{
int i;
int wait_cnt = 0;
if (action != PM_SUSPEND_PREPARE)
return NOTIFY_DONE;
JPEG_LOG(0, "action:%ld", action);
switch (action) {
case PM_SUSPEND_PREPARE:
mutex_lock(&jpeg_hybrid_dec_lock);
gJpegqDev.is_suspending = 1;
for (i = 0 ; i < HW_CORE_NUMBER; i++) {
JPEG_LOG(1, "jpeg dec sn wait core %d", i);
while (dec_hwlocked[i] && dec_hw_enable[i]) {
JPEG_LOG(1, "jpeg dec sn core %d locked. wait...", i);
usleep_range(10000, 20000);
wait_cnt++;
if (wait_cnt > 5) {
JPEG_LOG(0, "jpeg dec sn unlock core %d", i);
_jpeg_drv_hybrid_dec_unlock(i);
break;
}
mutex_lock(&jpeg_hybrid_dec_lock);
gJpegqDev.is_suspending = 1;
for (i = 0 ; i < HW_CORE_NUMBER; i++) {
JPEG_LOG(1, "jpeg dec sn wait core %d", i);
while (dec_hwlocked[i] && dec_hw_enable[i]) {
JPEG_LOG(1, "jpeg dec sn core %d locked. wait...", i);
usleep_range(10000, 20000);
wait_cnt++;
if (wait_cnt > 5) {
JPEG_LOG(0, "jpeg dec sn unlock core %d", i);
_jpeg_drv_hybrid_dec_unlock(i);
break;
}
}
mutex_unlock(&jpeg_hybrid_dec_lock);
return NOTIFY_OK;
case PM_POST_SUSPEND:
gJpegqDev.is_suspending = 0;
return NOTIFY_OK;
default:
return NOTIFY_DONE;
}
return NOTIFY_DONE;
mutex_unlock(&jpeg_hybrid_dec_lock);
return NOTIFY_OK;
}
static int jpeg_drv_hybrid_dec_post_suspend_notifier(
struct notifier_block *nb,
unsigned long action, void *data)
{
if (action != PM_POST_SUSPEND)
return NOTIFY_DONE;
JPEG_LOG(0, "action:%ld", action);
gJpegqDev.is_suspending = 0;
return NOTIFY_OK;
}
static int jpeg_drv_hybrid_dec_suspend(void)
@ -1310,8 +1316,16 @@ static int jpeg_probe(struct platform_device *pdev)
jpeg_drv_prepare_bw_request(node_index);
if (atomic_read(&nodeCount) == 1) {
gJpegqDev.pm_notifier.notifier_call = jpeg_drv_hybrid_dec_suspend_notifier;
register_pm_notifier(&gJpegqDev.pm_notifier);
gJpegqDev.pm_suspend_prepare_notifier.notifier_call =
jpeg_drv_hybrid_dec_suspend_prepare_notifier;
/* PM_SUSPEND_PREPARE priority should be higher than vcp */
gJpegqDev.pm_suspend_prepare_notifier.priority = 1;
register_pm_notifier(&gJpegqDev.pm_suspend_prepare_notifier);
gJpegqDev.pm_post_suspend_notifier.notifier_call =
jpeg_drv_hybrid_dec_post_suspend_notifier;
/* PM_POST_SUSPEND priority should be lower than vcp */
gJpegqDev.pm_post_suspend_notifier.priority = -1;
register_pm_notifier(&gJpegqDev.pm_post_suspend_notifier);
gJpegqDev.is_suspending = 0;
gJpegqDev.is_shutdowning = 0;
memset(_jpeg_hybrid_dec_int_status, 0, HW_CORE_NUMBER);

3
kernel/kernel_device_modules-6.6/drivers/misc/mediatek/jpeg/jpeg_drv.h
View File

@ -62,7 +62,8 @@ struct JpegDeviceStruct {
unsigned long jpeg_freqs[JPEG_LARB_COUNT][MAX_FREQ_STEP];
struct regulator *jpeg_reg[JPEG_LARB_COUNT];
struct clk *jpeg_dvfs[JPEG_LARB_COUNT];
struct notifier_block pm_notifier;
struct notifier_block pm_suspend_prepare_notifier;
struct notifier_block pm_post_suspend_notifier;
bool is_suspending;
bool is_shutdowning;
struct icc_path *jpeg_path_wdma[HW_CORE_NUMBER];

34
kernel/kernel_device_modules-6.6/drivers/misc/mediatek/performance/perf_ioctl/perf_ioctl_magt.c
View File

@ -350,7 +350,7 @@ static long magt_ioctl(struct file *filp,
}
query_mask = (1 << GET_FPSGO_PERF_IDX);
render = kcalloc(MAX_RENDER_TID, sizeof(struct render_frame_info), GFP_KERNEL);
render = kvmalloc(MAX_RENDER_TID * sizeof(struct render_frame_info), GFP_KERNEL);
if (!render) {
ret = -ENOMEM;
goto ret_ioctl;
@ -368,7 +368,7 @@ static long magt_ioctl(struct file *filp,
perfctl_copy_to_user((void *)arg, &pid_support, sizeof(struct fpsgo_pid_support));
ret = 0;
}
kfree(render);
kvfree(render);
break;
}
case MAGT_GET_FPSGO_STATUS:
@ -391,7 +391,7 @@ static long magt_ioctl(struct file *filp,
query_mask = (1 << GET_FPSGO_TARGET_FPS | 1 << GET_FPSGO_QUEUE_FPS
| 1 << GET_FRS_TARGET_FPS_DIFF | 1 << GET_GED_GPU_TIME);
render = kcalloc(MAX_RENDER_TID, sizeof(struct render_frame_info), GFP_KERNEL);
render = kvmalloc(MAX_RENDER_TID * sizeof(struct render_frame_info), GFP_KERNEL);
if (!render) {
ret = -ENOMEM;
goto ret_ioctl;
@ -411,7 +411,7 @@ static long magt_ioctl(struct file *filp,
if (render_item == -1) {
ret = -EINVAL;
kfree(render);
kvfree(render);
break;
}
render_status.curFps = render[render_item].queue_fps;
@ -421,7 +421,7 @@ static long magt_ioctl(struct file *filp,
perfctl_copy_to_user((void *)arg, &render_status, sizeof(struct fpsgo_render_status));
ret = 0;
}
kfree(render);
kvfree(render);
break;
}
case MAGT_GET_FPSGO_CRITICAL_THREAD_BG:
@ -441,7 +441,7 @@ static long magt_ioctl(struct file *filp,
}
query_mask = (1 << GET_FPSGO_MINITOP_LIST);
render = kcalloc(MAX_RENDER_TID, sizeof(struct render_frame_info), GFP_KERNEL);
render = kvmalloc(MAX_RENDER_TID * sizeof(struct render_frame_info), GFP_KERNEL);
if (!render) {
ret = -ENOMEM;
goto ret_ioctl;
@ -461,7 +461,7 @@ static long magt_ioctl(struct file *filp,
if (render_item == -1) {
ret = -EINVAL;
kfree(render);
kvfree(render);
break;
}
bg_info.bg_num = render[render_item].non_dep_num;
@ -474,7 +474,7 @@ static long magt_ioctl(struct file *filp,
perfctl_copy_to_user((void *)arg, &bg_info, sizeof(struct fpsgo_bg_info));
ret = 0;
}
kfree(render);
kvfree(render);
break;
}
case MAGT_GET_FPSGO_CPU_FRAMETIME:
@ -494,7 +494,7 @@ static long magt_ioctl(struct file *filp,
}
query_mask = (1 << GET_FPSGO_RAW_CPU_TIME | 1 << GET_FPSGO_EMA_CPU_TIME);
render = kcalloc(MAX_RENDER_TID, sizeof(struct render_frame_info), GFP_KERNEL);
render = kvmalloc(MAX_RENDER_TID * sizeof(struct render_frame_info), GFP_KERNEL);
if (!render) {
ret = -ENOMEM;
goto ret_ioctl;
@ -514,7 +514,7 @@ static long magt_ioctl(struct file *filp,
if (render_item == -1) {
ret = -EINVAL;
kfree(render);
kvfree(render);
break;
}
cpu_time_info.raw_t_cpu = render[render_item].raw_t_cpu;
@ -523,7 +523,7 @@ static long magt_ioctl(struct file *filp,
perfctl_copy_to_user((void *)arg, &cpu_time_info, sizeof(struct fpsgo_cpu_frametime));
ret = 0;
}
kfree(render);
kvfree(render);
break;
}
case MAGT_GET_FPSGO_THREAD_LOADING:
@ -543,7 +543,7 @@ static long magt_ioctl(struct file *filp,
}
query_mask = (1 << GET_FPSGO_AVG_FRAME_CAP | 1 << GET_FPSGO_DEP_LIST);
render = kcalloc(MAX_RENDER_TID, sizeof(struct render_frame_info), GFP_KERNEL);
render = kvmalloc(MAX_RENDER_TID * sizeof(struct render_frame_info), GFP_KERNEL);
if (!render) {
ret = -ENOMEM;
goto ret_ioctl;
@ -563,7 +563,7 @@ static long magt_ioctl(struct file *filp,
if (render_item == -1) {
ret = -EINVAL;
kfree(render);
kvfree(render);
break;
}
@ -577,7 +577,7 @@ static long magt_ioctl(struct file *filp,
perfctl_copy_to_user((void *)arg, &thread_loading, sizeof(struct fpsgo_thread_loading));
ret = 0;
}
kfree(render);
kvfree(render);
break;
}
case MAGT_GET_FPSGO_RENDER_PERFIDX:
@ -597,7 +597,7 @@ static long magt_ioctl(struct file *filp,
}
query_mask = (1 << GET_FPSGO_PERF_IDX);
render = kcalloc(MAX_RENDER_TID, sizeof(struct render_frame_info), GFP_KERNEL);
render = kvmalloc(MAX_RENDER_TID * sizeof(struct render_frame_info), GFP_KERNEL);
if (!render) {
ret = -ENOMEM;
goto ret_ioctl;
@ -617,14 +617,14 @@ static long magt_ioctl(struct file *filp,
if (render_item == -1) {
ret = -EINVAL;
kfree(render);
kvfree(render);
break;
}
render_perf.perf_idx = render[render_item].blc;
perfctl_copy_to_user((void *)arg, &render_perf, sizeof(struct fpsgo_render_perf));
ret = 0;
}
kfree(render);
kvfree(render);
break;
}
case MAGT_NOTIFY_THREAD_STATUS:

12
kernel/kernel_device_modules-6.6/drivers/misc/mediatek/sched/eas/group.c
View File

@ -340,9 +340,17 @@ static void group_init_tg_pointers(void)
struct cgroup_subsys_state *css = &root_task_group.css;
struct cgroup_subsys_state *top_css = css;
#ifdef CONFIG_OPLUS_SCHED_GROUP_OPT
oplus_update_tg_map(top_css, true);
#endif
rcu_read_lock();
css_for_each_child(css, top_css)
css_for_each_child(css, top_css) {
group_update_tg_pointer(css);
#ifdef CONFIG_OPLUS_SCHED_GROUP_OPT
oplus_update_tg_map(css, true);
#endif
}
rcu_read_unlock();
}
@ -389,7 +397,7 @@ static void group_android_rvh_cpu_cgroup_online(void *unused, struct cgroup_subs
group_update_tg_pointer(css);
#ifdef CONFIG_OPLUS_SCHED_GROUP_OPT
oplus_update_tg_map(css);
oplus_update_tg_map(css, false);
#endif
}

19
kernel/kernel_device_modules-6.6/drivers/misc/mediatek/sched/eas/sched_main.c
View File

@ -407,28 +407,29 @@ static void mtk_set_cpus_allowed_ptr(void *data, struct task_struct *p,
struct rq_flags rf;
struct cpumask *kernel_allowed_mask = &((struct mtk_task *) p->android_vendor_data1)->kernel_allowed_mask;
struct rq *rq = task_rq_lock(p, &rf);
cpumask_t new_mask;
cpumask_t user_mask;
// not set or invalid cpu mask
if (cpumask_empty(kernel_allowed_mask)){
goto out;
}
cpumask_copy(&user_mask, ctx->new_mask);
if (p->user_cpus_ptr &&
!(ctx->flags & (SCA_USER | SCA_MIGRATE_ENABLE | SCA_MIGRATE_DISABLE)) &&
cpumask_and(rq->scratch_mask, ctx->new_mask, p->user_cpus_ptr)) {
!(ctx->flags & (SCA_MIGRATE_ENABLE | SCA_MIGRATE_DISABLE)) &&
!((ctx->flags & SCA_USER) && (current->tgid != p->tgid))) {
*skip_user_ptr = true;
cpumask_copy(rq->scratch_mask, kernel_allowed_mask);
ctx->new_mask = rq->scratch_mask;
}
if (trace_sched_skip_user_enabled() && p->user_cpus_ptr && !cpumask_empty(kernel_allowed_mask)){
cpumask_copy(&new_mask, ctx->new_mask);
trace_sched_skip_user(p, *skip_user_ptr, p->user_cpus_ptr, kernel_allowed_mask, &new_mask);
}
if (trace_sched_skip_user_enabled() && p->user_cpus_ptr && !cpumask_empty(kernel_allowed_mask)) {
trace_sched_skip_user(p, *skip_user_ptr, &user_mask, kernel_allowed_mask, ctx->new_mask);
}
out:
task_rq_unlock(rq, p, &rf);
return;
task_rq_unlock(rq, p, &rf);
return;
}
#if IS_ENABLED(CONFIG_MTK_IRQ_MONITOR_DEBUG)

19
kernel/kernel_device_modules-6.6/drivers/misc/mediatek/typec/tcpc/tcpci_typec.c
View File

@ -915,6 +915,7 @@ static inline bool typec_cc_change_source_entry(struct tcpc_device *tcpc)
static inline bool typec_attached_snk_cc_change(struct tcpc_device *tcpc)
{
uint8_t cc_res = typec_get_cc_res();
bool changed = false;
#if IS_ENABLED(CONFIG_USB_POWER_DELIVERY)
struct pd_port *pd_port = &tcpc->pd_port;
#endif /* CONFIG_USB_POWER_DELIVERY */
@ -922,20 +923,21 @@ static inline bool typec_attached_snk_cc_change(struct tcpc_device *tcpc)
if (cc_res != tcpc->typec_remote_rp_level) {
TYPEC_INFO("RpLvl Change\n");
tcpc->typec_remote_rp_level = cc_res;
changed = true;
}
#if CONFIG_USB_PD_REV30
if (pd_port->pe_data.pd_connected && pd_check_rev30(pd_port) &&
cc_res == TYPEC_CC_VOLT_SNK_3_0)
pd_put_sink_tx_event(tcpc, cc_res);
if (pd_port->pe_data.pd_connected && pd_check_rev30(pd_port) &&
cc_res == TYPEC_CC_VOLT_SNK_3_0)
pd_put_sink_tx_event(tcpc, cc_res);
#endif /* CONFIG_USB_PD_REV30 */
if (changed) {
#if IS_ENABLED(CONFIG_USB_POWER_DELIVERY)
if (!pd_port->pe_data.pd_connected)
#endif /* CONFIG_USB_POWER_DELIVERY */
tcpci_sink_vbus(tcpc,
TCP_VBUS_CTRL_TYPEC, TCPC_VBUS_SINK_5V, -1);
TCP_VBUS_CTRL_TYPEC, TCPC_VBUS_SINK_5V, -1);
}
return true;
}
@ -1051,11 +1053,6 @@ static inline void typec_attach_wait_entry(struct tcpc_device *tcpc)
case typec_attached_dbgacc_snk:
#endif /* CONFIG_TYPEC_CAP_DBGACC_SNK */
case typec_attached_custom_src:
if (cc_res == tcpc->typec_remote_rp_level) {
tcpc_reset_typec_debounce_timer(tcpc);
TYPEC_DBG("The Same RpLvl, Ignore cc_attach\n");
return;
}
TYPEC_INFO("RpLvl Alert\n");
#if CONFIG_USB_PD_REV30
if (pd_port->pe_data.pd_connected && pd_check_rev30(pd_port) &&

94
kernel/kernel_device_modules-6.6/drivers/phy/mediatek/phy-mtk-xsphy.c
View File

@ -81,6 +81,12 @@
#define P2A5_RG_HSTX_SRCAL_EN BIT(15)
#define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12)
//mtk_debug
#define P2A6_RG_USB20_SQD GENMASK(23, 22)
#define P2A5_RG_USB20_SQD_VAL(x) ((0x3 & (x)) << 22)
#define P2A5_RG_USB20_SQD_MASK (0x3)
#define P2A5_RG_USB20_SQD_OFET (22)
#define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
#define P2A6_RG_U2_PHY_REV6 GENMASK(31, 30)
#define P2A6_RG_U2_PHY_REV6_VAL(x) ((0x3 & (x)) << 30)
@ -296,6 +302,8 @@
#define PHY_REV6_STR "phy_rev6"
#define DISCTH_STR "discth"
#define RX_SQTH_STR "rx_sqth"
#define RX_SQD_STR "rx_sqd"
#define INTR_OFS_STR "intr_ofs"
#define TERM_OFS_STR "term_ofs"
#define SIB_STR "sib"
@ -415,6 +423,8 @@ struct xsphy_instance {
int discth;
int rx_sqth;
int host_rx_sqth;
int rx_sqd;
int host_rx_sqd;
int rev6;
int hsrx_vref_sel;
int fs_cr;
@ -1243,6 +1253,63 @@ static const struct proc_ops proc_rx_sqth_fops = {
.proc_release = single_release,
};
static int proc_rx_sqd_show(struct seq_file *s, void *unused)
{
struct xsphy_instance *inst = s->private;
void __iomem *pbase = inst->port_base;
u32 tmp;
char str[16];
tmp = readl(pbase + XSP_USBPHYACR5);
tmp >>= P2A5_RG_USB20_SQD_OFET;
tmp &= P2A5_RG_USB20_SQD_MASK;
cover_val_to_str(tmp, 4, str);
seq_printf(s, "\n%s = %s\n", RX_SQD_STR, str);
return 0;
}
static int proc_rx_sqd_open(struct inode *inode, struct file *file)
{
return single_open(file, proc_rx_sqd_show, pde_data(inode));
}
static ssize_t proc_rx_sqd_write(struct file *file,
const char __user *ubuf, size_t count, loff_t *ppos)
{
struct seq_file *s = file->private_data;
struct xsphy_instance *inst = s->private;
void __iomem *pbase = inst->port_base;
char buf[20];
u32 val;
memset(buf, 0x00, sizeof(buf));
if (count > sizeof(buf) - 1)
return -EINVAL;
if (copy_from_user(&buf, ubuf, count))
return -EFAULT;
if (kstrtouint(buf, 2, &val))
return -EINVAL;
inst->rx_sqd = val;
inst->host_rx_sqd = val;
mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A6_RG_USB20_SQD, val);
return count;
}
static const struct proc_ops proc_rx_sqd_fops = {
.proc_open = proc_rx_sqd_open,
.proc_write = proc_rx_sqd_write,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
};
static int proc_intr_ofs_show(struct seq_file *s, void *unused)
{
struct xsphy_instance *inst = s->private;
@ -1447,6 +1514,14 @@ static int u2_phy_procfs_init(struct mtk_xsphy *xsphy,
goto err1;
}
file = proc_create_data(RX_SQD_STR, 0640,
phy_root, &proc_rx_sqd_fops, inst);
if (!file) {
dev_info(dev, "failed to creat proc file: %s\n", RX_SQD_STR);
ret = -ENOMEM;
goto err1;
}
file = proc_create_data(INTR_OFS_STR, 0640,
phy_root, &proc_intr_ofs_fops, inst);
if (!file) {
@ -2688,6 +2763,12 @@ static void phy_parse_property(struct mtk_xsphy *xsphy,
if (device_property_read_u32(dev, "mediatek,host-rx-sqth",
&inst->host_rx_sqth) || inst->host_rx_sqth < 0)
inst->host_rx_sqth = -EINVAL;
if (device_property_read_u32(dev, "mediatek,rx-sqd",
&inst->rx_sqd) || inst->rx_sqd < 0)
inst->rx_sqd = -EINVAL;
if (device_property_read_u32(dev, "mediatek,host-rx-sqd",
&inst->host_rx_sqd) || inst->host_rx_sqd < 0)
inst->host_rx_sqd = -EINVAL;
if (device_property_read_u32(dev, "mediatek,rev6",
&inst->rev6) || inst->rev6 < 0)
inst->rev6 = -EINVAL;
@ -2746,9 +2827,9 @@ static void phy_parse_property(struct mtk_xsphy *xsphy,
dev_dbg(dev, "src_host:%d, vrt_host:%d, term_host:%d\n",
inst->eye_src_host, inst->eye_vrt_host,
inst->eye_term_host);
dev_dbg(dev, "discth:%d, rx_sqth:%d, host_rx_sqth:%d, rev6:%d, rev6_host:%d\n",
dev_dbg(dev, "discth:%d, rx_sqth:%d, host_rx_sqth:%d, rev6:%d, rev6_host:%d, rx_sqd:%d, host_rx_sqd:%d\n",
inst->discth, inst->rx_sqth, inst->host_rx_sqth, inst->rev6,
inst->rev6_host);
inst->rev6_host, inst->rx_sqd, inst->host_rx_sqd);
dev_dbg(dev, "u2-sw-efuse:%d hwpll-mode:%d, refclk-sel:%d, chp-en-disable:%d",
inst->u2_sw_efuse, inst->hwpll_mode, inst->refclk_sel, inst->chp_en_disable);
#ifdef OPLUS_FEATURE_CHG_BASIC
@ -2862,6 +2943,10 @@ static void u2_phy_props_set(struct mtk_xsphy *xsphy,
mtk_phy_update_field(pbase + XSP_USBPHYACR6, P2A6_RG_U2_SQTH,
inst->rx_sqth);
if (inst->rx_sqd != -EINVAL)
mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A6_RG_USB20_SQD,
inst->rx_sqd);
if (inst->rev6 != -EINVAL)
mtk_phy_update_field(pbase + XSP_USBPHYACR6, P2A6_RG_U2_PHY_REV6,
inst->rev6);
@ -2917,6 +3002,10 @@ static void u2_phy_host_props_set(struct mtk_xsphy *xsphy,
mtk_phy_update_field(pbase + XSP_USBPHYACR6, P2A6_RG_U2_SQTH,
inst->host_rx_sqth);
if (inst->host_rx_sqd != -EINVAL)
mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A6_RG_USB20_SQD,
inst->host_rx_sqd);
if (inst->eye_src_host != -EINVAL)
mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
inst->eye_src_host);
@ -3015,6 +3104,7 @@ static int mtk_phy_init(struct phy *phy)
dev_info(xsphy->dev, "term_cal:%d term_ofs:%d host_term_ofs:%d\n",
inst->efuse_term_cal, inst->term_ofs, inst->host_term_ofs);
dev_info(xsphy->dev, "rx_sqth:%d host_rx_sqth:%d\n", inst->rx_sqth, inst->host_rx_sqth);
dev_info(xsphy->dev, "rx_sqd:%d host_rx_sqd:%d\n", inst->rx_sqd, inst->host_rx_sqd);
dev_info(xsphy->dev, "pll_fbksel:%d, pll_posdiv: %d\n",
inst->pll_fbksel, inst->pll_posdiv);
break;

4
kernel/kernel_device_modules-6.6/drivers/power/supply/mt6358-gauge.c
View File

@ -821,7 +821,11 @@ static int get_nafg_vbat(struct mtk_gauge *gauge)
AUXADC_ADC_OUT_NAG_SHIFT)) >> AUXADC_ADC_OUT_NAG_SHIFT;
if ((nag_vbat_reg & 0x8000) != 0)
break;
#ifdef OPLUS_FEATURE_CHG_BASIC
msleep(2);
#else
msleep(30);
#endif
i++;
} while (i <= 5);

29
kernel/kernel_device_modules-6.6/drivers/ufs/ufs-mediatek-dbg.c
View File

@ -36,7 +36,7 @@
#endif
#define MAX_CMD_HIST_ENTRY_CNT (500)
#define UFS_AEE_BUFFER_SIZE (100 * 1024)
#define UFS_AEE_BUFFER_SIZE (128 * 1024)
/*
* Currently only global variables are used.
@ -420,6 +420,30 @@ static void ufs_mtk_dbg_print_info(char **buff, unsigned long *size,
UFS_EVT_ABORT, "task_abort");
}
static void oplus_block_dbg_print_info(char **buff, unsigned long *size,
struct seq_file *m)
{
int i;
struct ufs_hba *hba = ufshba;
struct Scsi_Host *shost = hba->host;
struct blk_mq_tag_set *tag_set = &shost->tag_set;
if (tag_set->shared_tags) {
struct blk_mq_tags *tags = tag_set->shared_tags;
for (i = 0; i < tags->nr_tags; i++) {
struct request *rq = tags->static_rqs[i];
if (!rq)
continue;
/* Block Request Information */
SPREAD_PRINTF(buff, size, m,
"Request Infomation:t=%d,it=%d,dl=%d,s=%lld,atn=%lld,stn=%lld,istn=%lld\n", rq->tag, rq->internal_tag, rq->__data_len, rq->__sector, rq->alloc_time_ns, rq->start_time_ns, rq->io_start_time_ns);
}
} else {
SPREAD_PRINTF(buff, size, m,
"Request Information Obtain Fail!\n");
}
}
static int cmd_hist_get_entry(void)
{
unsigned long flags;
@ -2148,6 +2172,7 @@ void ufs_mtk_dbg_get_aee_buffer(unsigned long *vaddr, unsigned long *size)
ufs_mtk_dbg_print_info(&buff, &free_size, NULL);
ufs_mtk_dbg_print_cmd_hist(&buff, &free_size,
MAX_CMD_HIST_ENTRY_CNT, NULL, false);
oplus_block_dbg_print_info(&buff, &free_size, NULL);
/* retrun start location */
*vaddr = (unsigned long)ufs_aee_buffer;
@ -2212,6 +2237,8 @@ static int ufs_debug_proc_show(struct seq_file *m, void *v)
ufs_mtk_dbg_print_info(NULL, NULL, m);
ufs_mtk_dbg_print_cmd_hist(NULL, NULL, MAX_CMD_HIST_ENTRY_CNT,
m, false);
oplus_block_dbg_print_info(NULL, NULL, m);
return 0;
}

3
kernel/oplus/bazel/oplus_modules_list.bzl
View File

@ -72,9 +72,7 @@ COMMON_OPLUS_MODULES_LIST = [
"//vendor/oplus/kernel/camera:oplus_camera_jd5516w",
"//vendor/oplus/kernel/camera:oplus_camera_jd5516w_24618",
"//vendor/oplus/kernel/camera:oplus_camera_jd5516we4",
"//vendor/oplus/kernel/camera:oplus_camera_dw9786",
"//vendor/oplus/kernel/camera:oplus_camera_ak7316t33",
"//vendor/oplus/kernel/camera:oplus_camera_ois_dw9786",
"//vendor/oplus/kernel/camera:oplus_camera_ois_power",
"//vendor/oplus/kernel/camera:oplus_camera_aw36515_brza",
"//vendor/oplus/kernel/cpu/game_opt:oplus_bsp_game_opt",
@ -114,6 +112,7 @@ COMMON_OPLUS_MODULES_LIST = [
"//vendor/oplus/kernel/mm:oplus_bsp_zram_opt",
#"//vendor/oplus/kernel/mm:oplus_bsp_look_around",
"//vendor/oplus/kernel/mm:oplus_bsp_kshrink_slabd",
"//vendor/oplus/kernel/mm:oplus_bsp_zstdn",
"//vendor/oplus/kernel/synchronize:oplus_lock_torture",
"//vendor/oplus/kernel/wifi:oplus_connectivity_routerboost",
"//vendor/oplus/kernel/wifi:oplus_connectivity_sla",

BIN
kernel/oplus/tools/config_info.xlsx
View File

Binary file not shown.

BIN
kernel/oplus/tools/ko_owner_list.xlsx
View File

Binary file not shown.

9
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/Kbuild.main vendored
View File

@ -440,6 +440,7 @@ CONFIG_MTK_WIFI_SUPPORT_TXPWR_ENV=y
CONFIG_MTK_WIFI_SUPPORT_6G_PWR_MODE=y
CONFIG_WIFI_RAM_HW_DETECT_REPORT_SUPPORT=y
CONFIG_WIFI_PLAT_SHUTDOWN_SUPPORT=y
ifneq ($(filter 6983 6895 6879 6886, $(WLAN_CHIP_ID)),)
CONFIG_RX_NAPI_THREADED=n
else
@ -473,6 +474,8 @@ else
ifneq ($(filter 6897 6878 6899, $(WLAN_CHIP_ID)),)
ccflags-y += -DCFG_WLAN_LK_FWDL_SUPPORT=1
ccflags-y += -DCFG_WLAN_ATF_SUPPORT=0
CONFIG_MTK_WIFI_DRVOWN_EINT_CHECK=y
ccflags-y += -DCFG_MTK_WIFI_FORCE_HOST_CSR_IRQ_EN
endif
endif
@ -1280,6 +1283,12 @@ else
ccflags-y += -DCFG_SUPPORT_DISABLE_CMD_DDONE_INTR=0
endif
ifeq ($(CONFIG_MTK_WIFI_DRVOWN_EINT_CHECK), y)
ccflags-y += -DCFG_CHECK_DRVOWN_EINT=1
else
ccflags-y += -DCFG_CHECK_DRVOWN_EINT=0
endif
ifeq ($(CONFIG_MTK_WIFI_CONNAC2X), y)
ccflags-y += -DCFG_SUPPORT_CONNAC2X=1
else

80
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/chips/common/cmm_asic_connac2x.c vendored
View File

@ -1207,22 +1207,78 @@ void asicConnac2xLowPowerOwnClear(
u_int8_t *pfgResult)
{
struct mt66xx_chip_info *prChipInfo;
uint32_t u4RegValue = 0;
#if (CFG_CHECK_DRVOWN_EINT == 1)
uint32_t u4Retry = 0;
#endif
prChipInfo = prAdapter->chip_info;
if (prChipInfo->is_support_asic_lp) {
u_int32_t u4RegValue = 0;
HAL_MCR_WR(prAdapter,
CONNAC2X_BN0_LPCTL_ADDR,
PCIE_LPCR_HOST_CLR_OWN);
HAL_MCR_RD(prAdapter,
CONNAC2X_BN0_LPCTL_ADDR,
&u4RegValue);
*pfgResult = (u4RegValue &
PCIE_LPCR_AP_HOST_OWNER_STATE_SYNC) == 0;
} else
if (!prChipInfo->is_support_asic_lp) {
*pfgResult = TRUE;
return;
}
#if IS_ENABLED(CFG_MTK_WIFI_FORCE_HOST_CSR_IRQ_EN)
if (prChipInfo->forceEnableHostCsrIrq)
prChipInfo->forceEnableHostCsrIrq(prAdapter);
#endif
#if (CFG_CHECK_DRVOWN_EINT == 1)
while (1) {
/* EINT CR select */
/* WR 0x7c06_0B00[0] = 0x1 */
HAL_MCR_RD(prAdapter, 0x7c060B00, &u4RegValue);
u4RegValue |= 0x1;
HAL_MCR_WR(prAdapter, 0x7c060B00, u4RegValue);
/* WR 0x7c06_0B04[4:0] = 0x6 */
HAL_MCR_RD(prAdapter, 0x7c060B04, &u4RegValue);
u4RegValue &= ~BITS(0, 4);
u4RegValue |= 0x6;
HAL_MCR_WR(prAdapter, 0x7c060B04, u4RegValue);
/* WR 0x7c06_0B14[2:0] = 0x1 */
HAL_MCR_RD(prAdapter, 0x7c060B14, &u4RegValue);
u4RegValue &= ~BITS(0, 2);
u4RegValue |= 0x1;
HAL_MCR_WR(prAdapter, 0x7c060B14, u4RegValue);
/* Check MCU wake, RD 0x7c06_0A10[4] */
HAL_MCR_RD(prAdapter, 0x7c060A10, &u4RegValue);
/* Clear FW own */
HAL_MCR_WR(prAdapter,
CONNAC2X_BN0_LPCTL_ADDR, PCIE_LPCR_HOST_CLR_OWN);
if (!(u4RegValue & BIT(4))) {
kalUdelay(LP_OWN_EINT_CHECK_DELAY);
} else {
DBGLOG(HAL, TRACE, "MCU not in sleep (0x%08x)\n",
u4RegValue);
break;
}
/* Check EINT, RD 0x7c06_0B10 (WF_AON_DBG_FLAG) */
HAL_MCR_RD(prAdapter, 0x7c060B10, &u4RegValue);
if (((u4RegValue & BIT(0)) != 0)
&& ((u4RegValue & BIT(10)) != 0)) {
DBGLOG(HAL, ERROR,
"EINT trigger failed [0x%08x]\n", u4RegValue);
if (u4Retry == LP_OWN_EINT_CHECK_RETRY_CNT)
break;
u4Retry++;
} else
break;
}
#else /* !CFG_CHECK_DRVOWN_EINT */
HAL_MCR_WR(prAdapter,
CONNAC2X_BN0_LPCTL_ADDR, PCIE_LPCR_HOST_CLR_OWN);
#endif /* CFG_CHECK_DRVOWN_EINT */
HAL_MCR_RD(prAdapter,
CONNAC2X_BN0_LPCTL_ADDR, &u4RegValue);
*pfgResult = (u4RegValue &
PCIE_LPCR_AP_HOST_OWNER_STATE_SYNC) == 0;
}
void asicConnac2xProcessSoftwareInterrupt(

15
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/chips/common/dbg_connac2x.c vendored
View File

@ -3401,6 +3401,11 @@ void connac2x_show_wfdma_info(struct ADAPTER *prAdapter)
struct SW_WFDMA_INFO *prSwWfdmaInfo;
uint32_t u4DmaNum = 1;
if (!prAdapter) {
DBGLOG(HAL, ERROR, "prAdapter NULL\n");
return;
}
prChipInfo = prAdapter->chip_info;
prBusInfo = prChipInfo->bus_info;
prSwWfdmaInfo = &prBusInfo->rSwWfdmaInfo;
@ -3444,6 +3449,11 @@ void connac2x_show_dmashdl_info(struct ADAPTER *prAdapter)
DBGLOG(HAL, INFO, "DMASHDL info:\n");
if (!prAdapter) {
DBGLOG(HAL, ERROR, "prAdapter NULL\n");
return;
}
prBusInfo = prAdapter->chip_info->bus_info;
prCfg = prBusInfo->prDmashdlCfg;
@ -3898,6 +3908,11 @@ void connac2x_show_pse_info(struct ADAPTER *prAdapter)
char *str;
uint32_t pse_peek[10] = {0};
if (!prAdapter) {
DBGLOG(HAL, ERROR, "prAdapter NULL\n");
return;
}
prBusInfo = prAdapter->chip_info->bus_info;
pse_group = prBusInfo->prPseGroup;
prCr = prBusInfo->prPseTopCr;

121
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/chips/soc7_0/soc7_0.c vendored
View File

@ -119,6 +119,14 @@ static u_int8_t soc7_0_get_sw_interrupt_status(struct ADAPTER *prAdapter,
static void soc7_0_DumpWfsyscpupcr(struct ADAPTER *prAdapter);
#if (CFG_CHECK_DRVOWN_EINT == 1)
static void soc7_0_CheckDrvownEint(struct ADAPTER *prAdapter);
#endif
#if IS_ENABLED(CFG_MTK_WIFI_FORCE_HOST_CSR_IRQ_EN)
static void soc7_0ForceEnableHostCsrIrq(struct ADAPTER *prAdapter);
#endif
static uint32_t soc7_0_SetupRomEmi(struct ADAPTER *prAdapter);
static void soc7_0_SetupFwDateInfo(struct ADAPTER *prAdapter,
enum ENUM_IMG_DL_IDX_T eDlIdx,
@ -732,6 +740,9 @@ struct mt66xx_chip_info mt66xx_chip_info_soc7_0 = {
.fw_log_info = {
.ops = &soc7_0_fw_log_ops,
},
#if IS_ENABLED(CFG_MTK_WIFI_FORCE_HOST_CSR_IRQ_EN)
.forceEnableHostCsrIrq = soc7_0ForceEnableHostCsrIrq,
#endif
};
struct mt66xx_hif_driver_data mt66xx_driver_data_soc7_0 = {
@ -1646,6 +1657,27 @@ static int wf_pwr_on_consys_mcu(struct ADAPTER *prAdapter)
value |= 0x00000100;
wf_ioremap_write(DEBUG_CTRL_AO_WFMCU_PWA_CTRL3, value);
#if (CFG_CHECK_DRVOWN_EINT == 1)
/* Set conn2wf remapping window
* Address: 0x830C_0120
* Data: 32'h81050000
* Action: write
*/
kalDevRegWrite(NULL, WF_MCU_BUS_CR_AP2WF_REMAP_1_ADDR,
0x81050000);
/* Set cirq IRQ_DBGSEL for dump eint status
* Address: 0x1850_00F4[7:0]
* Data: 8'h80
* Action: write
*/
wf_ioremap_read(0x185000f4, &value);
value &= 0xffffff00;
value |= 0x00000080;
wf_ioremap_write(0x185000f4, value);
wf_ioremap_read(0x185000f4, &value);
#endif
/* Enable wfsys bus timeout (debug ctrl ao)
* Address: 0x1850_0000[4] 0x1850_0000[3] 0x1850_0000[2]
* Data: 1'b1 1'b1 1'b1
@ -2115,6 +2147,9 @@ static uint32_t soc7_0_McuInit(struct ADAPTER *prAdapter)
"wf_pwr_on_consys_mcu failed, ret=%d\n",
ret);
soc7_0_DumpBusHangCr(prAdapter);
glSetRstReasonString(
"wlan polling mcu idle fail");
glResetWholeChipResetTrigger(g_reason);
goto exit;
}
@ -2293,6 +2328,88 @@ static void soc7_0_DumpWfsyscpupcr(struct ADAPTER *prAdapter)
log_buf_lp[4]);
}
#if (CFG_CHECK_DRVOWN_EINT == 1)
static void soc7_0_CheckDrvownEint(struct ADAPTER *prAdapter)
{
u_int32_t u4RegValue = 0;
/* WR 0x1806_0B00[0] = 0x1 */
HAL_MCR_RD(prAdapter, 0x7c060B00, &u4RegValue);
u4RegValue |= 0x1;
HAL_MCR_WR(prAdapter, 0x7c060B00, u4RegValue);
/* WR 0x1806_0B04[4:0] = 0x6 */
HAL_MCR_RD(prAdapter, 0x7c060B04, &u4RegValue);
u4RegValue &= ~BITS(0, 4);
u4RegValue |= 0x6;
HAL_MCR_WR(prAdapter, 0x7c060B04, u4RegValue);
/* WR 0x1806_0B14[2:0] = 0x1 */
HAL_MCR_RD(prAdapter, 0x7c060B14, &u4RegValue);
u4RegValue &= ~BITS(0, 2);
u4RegValue |= 0x1;
HAL_MCR_WR(prAdapter, 0x7c060B14, u4RegValue);
/* RD 0x1806_0B10 (WF_AON_DBG_FLAG) */
HAL_MCR_RD(prAdapter, 0x7c060B10, &u4RegValue);
}
#endif
#if IS_ENABLED(CFG_MTK_WIFI_FORCE_HOST_CSR_IRQ_EN)
static void soc7_0ForceEnableHostCsrIrq(struct ADAPTER *prAdapter)
{
uint32_t u4RegValue = 0, u4ConnsysVersion = kalGetConnsysVersion();
uint8_t ucPollingCnt = 0;
/* wake up conn_infra */
HAL_MCR_RD(prAdapter, 0x7c0601a4, &u4RegValue);
u4RegValue |= BIT(0);
HAL_MCR_WR(prAdapter, 0x7c0601a4, u4RegValue);
kalUdelay(200);
/* check conn_infra off ID */
while (1) {
kalMdelay(1);
HAL_MCR_RD(prAdapter, 0x7c011000, &u4RegValue);
if (u4RegValue == u4ConnsysVersion)
break;
if (ucPollingCnt >= 10) {
DBGLOG(HAL, ERROR,
"Polling conn_infra ID failed. (0x%08x)\n",
u4RegValue);
return;
}
ucPollingCnt++;
}
/* check conn_infra cmdbt restore done */
ucPollingCnt = 0;
while (1) {
kalUdelay(500);
HAL_MCR_RD(prAdapter, 0x7c001210, &u4RegValue);
if ((u4RegValue & BIT(16)) == BIT(16))
break;
if (ucPollingCnt >= 10) {
DBGLOG(HAL, ERROR,
"conn_infra cmdbt restore failed.(0x%08x)\n",
u4RegValue);
return;
}
ucPollingCnt++;
}
/* force enable HOST_CSR_IRQ_EN */
HAL_MCR_RD(prAdapter, 0x7c001600, &u4RegValue);
HAL_MCR_WR(prAdapter, 0x7c001600, 0x3FF);
HAL_MCR_RD(prAdapter, 0x7c001600, &u4RegValue);
/* let conn_infra sleep */
HAL_MCR_RD(prAdapter, 0x7c0601a4, &u4RegValue);
u4RegValue &= ~0x1;
HAL_MCR_WR(prAdapter, 0x7c0601a4, u4RegValue);
}
#endif
static void soc7_0_DumpPcLrLog(struct ADAPTER *prAdapter)
{
#define HANG_PC_LOG_NUM 32
@ -2558,6 +2675,10 @@ static void soc7_0_DumpOtherCr(struct ADAPTER *prAdapter)
connac2x_DbgCrRead(prAdapter, 0x18400120, &u4Val);
DBGLOG(INIT, INFO, "0x18400120=[0x%08x]\n", u4Val);
#if (CFG_CHECK_DRVOWN_EINT == 1)
soc7_0_CheckDrvownEint(prAdapter);
#endif
set_wf_monflg_on_mailbox_wf();
/* pooling host_mailbox_wf status */

6
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/common/wlan_lib.c vendored
View File

@ -8209,8 +8209,10 @@ void wlanInitFeatureOptionImpl(struct ADAPTER *prAdapter, uint8_t *pucKey)
#if CFG_SUPPORT_RX_NAPI
/* unit: s */
INIT_UINT(prWifiVar->u4NapiScheduleTimeout, "NapiScheduleTimeout", 60,
FEATURE_TO_CUSTOMER);
INIT_UINT(prWifiVar->u4NapiScheduleTimeout, "NapiScheduleTimeout",
60, FEATURE_DEBUG_ONLY);
INIT_UINT(prWifiVar->fgNapiScheduleAeeEn, "NapiScheduleAeeEn",
FEATURE_DISABLED, FEATURE_DEBUG_ONLY);
#endif
#if CFG_NAPI_DELAY

678
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/include/mgmt/oplus_rlm_txpwr_init_lmt.h vendored
View File

File diff suppressed because it is too large Load Diff

1
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/include/mgmt/p2p_dev.h vendored
View File

@ -125,6 +125,7 @@ struct P2P_PENDING_MGMT_INFO {
enum ENUM_BAND eBand;
uint8_t ucChannelNum;
uint8_t fgIsOffChannel;
uint8_t ucBssIdx;
};
struct P2P_DEV_FSM_INFO {

13
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/include/mgmt/p2p_func.h vendored
View File

@ -156,6 +156,16 @@ uint32_t
p2pFuncIsPendingTxMgmtNeedWait(struct ADAPTER *prAdapter, uint8_t ucRoleIndex,
enum ENUM_P2P_MGMT_TX_TYPE eP2pMgmtTxType);
enum ENUM_P2P_CONNECT_STATE
p2pFuncTagMgmtFrame(struct MSDU_INFO *prMgmtTxMsdu,
uint64_t u8Cookie);
u_int8_t
p2pFuncGetBssIdxByCookie(struct ADAPTER *prAdapter,
uint8_t ucRoleIndex,
struct P2P_PENDING_MGMT_INFO **prPendingMgmtInfoValid,
uint64_t u8cookie);
void p2pFuncAcquireCh(struct ADAPTER *prAdapter,
uint8_t ucBssIdx,
struct P2P_CHNL_REQ_INFO *prChnlReqInfo);
@ -661,6 +671,9 @@ p2pFuncNeedWaitRsp(struct ADAPTER *prAdapter,
u_int8_t
p2pFuncNeedForceSleep(struct ADAPTER *prAdapter);
u_int8_t
p2pFuncIsSapGoCsa(struct ADAPTER *prAdapter, uint8_t ucRoleIdx);
void
p2pFunClearAllTxReq(struct ADAPTER *prAdapter,
struct P2P_MGMT_TX_REQ_INFO *prP2pMgmtTxInfo);

1
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/include/nic/adapter.h vendored
View File

@ -1266,6 +1266,7 @@ struct WIFI_VAR {
uint32_t u4PerfMonTpTh[PERF_MON_TP_MAX_THRESHOLD];
#if CFG_SUPPORT_RX_NAPI
uint32_t u4NapiScheduleTimeout;
u_int8_t fgNapiScheduleAeeEn;
#endif
#if CFG_NAPI_DELAY
uint32_t u4NapiDelayTputTh;

4
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/include/nic/mt66xx_reg.h vendored
View File

@ -1709,6 +1709,10 @@ struct mt66xx_chip_info {
uint8_t ucBssidx);
#endif
#if IS_ENABLED(CFG_MTK_WIFI_FORCE_HOST_CSR_IRQ_EN)
void (*forceEnableHostCsrIrq)(struct ADAPTER *prAdapter);
#endif
/* If you want to explicitly specify the max AMPDU length exponent in
* HE CAP IE instead of using default one specified by
* prWifiVar->ucMaxAmpduLenExp, then you shall set

1
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/include/nic/nic_rx.h vendored
View File

@ -555,6 +555,7 @@ enum ENUM_RX_STATISTIC_COUNTER {
RX_TASKLET_COUNT,
RX_WORK_COUNT,
RX_NAPI_SCHEDULE_COUNT,
RX_NAPI_SCHEDULE_FAIL_COUNT,
RX_NAPI_LEGACY_SCHED_COUNT,
RX_NAPI_WORK_COUNT,
RX_NAPI_POLL_COUNT,

2
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/include/precomp.h vendored
View File

@ -227,9 +227,9 @@
#include "p2p_ie.h"
#include "p2p_role.h"
#include "p2p_func.h"
#include "p2p_scan.h"
#include "p2p_dev.h"
#include "p2p_func.h"
#include "p2p_fsm.h"
#include "p2p_link.h"
#endif

2
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/include/pwr_mgt.h vendored
View File

@ -49,6 +49,8 @@
#define LP_OWN_BACK_LOOP_DELAY_MIN_US 900
#define LP_OWN_BACK_LOOP_DELAY_MAX_US 1000
#define LP_OWN_REQ_CLR_INTERVAL_MS 200
#define LP_OWN_EINT_CHECK_DELAY 156 /* 5T 32K = 0.156ms */
#define LP_OWN_EINT_CHECK_RETRY_CNT 2
#define LP_DBGCR_POLL_ROUND 1
/*******************************************************************************

40
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/mgmt/p2p_func.c vendored
View File

@ -782,6 +782,8 @@ p2pFuncAddPendingMgmtLinkEntry(struct ADAPTER *prAdapter,
prPendingMgmtInfo->ucChannelNum =
prMgmtTxMsg->rChannelInfo.ucChannelNum;
prPendingMgmtInfo->fgIsOffChannel = prMgmtTxMsg->fgIsOffChannel;
prPendingMgmtInfo->ucBssIdx = prMgmtTxMsg->ucBssIdx;
LINK_INSERT_TAIL(&prGlueP2pInfo->rWaitTxDoneLink,
&prPendingMgmtInfo->rLinkEntry);
@ -1212,6 +1214,30 @@ p2pFuncTagMgmtFrame(struct MSDU_INFO *prMgmtTxMsdu,
return eCNNState;
}
u_int8_t
p2pFuncGetBssIdxByCookie(struct ADAPTER *prAdapter,
uint8_t ucRoleIndex,
struct P2P_PENDING_MGMT_INFO **prPendingMgmtInfoValid,
uint64_t u8cookie)
{
struct GL_P2P_INFO *prGlueP2pInfo = NULL;
struct P2P_PENDING_MGMT_INFO *prPendingMgmtInfo = NULL;
struct P2P_PENDING_MGMT_INFO *prPendingMgmtInfoNext = NULL;
prGlueP2pInfo = prAdapter->prGlueInfo->prP2PInfo[ucRoleIndex];
LINK_FOR_EACH_ENTRY_SAFE(prPendingMgmtInfo,
prPendingMgmtInfoNext, &prGlueP2pInfo->rWaitTxDoneLink,
rLinkEntry, struct P2P_PENDING_MGMT_INFO) {
if (prPendingMgmtInfoNext->u8PendingMgmtCookie
== u8cookie) {
*prPendingMgmtInfoValid = prPendingMgmtInfoNext;
return TRUE;
}
}
return FALSE;
}
struct MSDU_INFO *p2pFuncProcessAuth(
struct ADAPTER *prAdapter,
struct STA_RECORD *prStaRec,
@ -4309,6 +4335,11 @@ p2pFuncValidateAuth(struct ADAPTER *prAdapter,
"Current OP mode is not under AP mode. (%d)\n",
prP2pBssInfo->eCurrentOPMode);
return FALSE;
} else if (p2pFuncIsSapGoCsa(prAdapter, prP2pBssInfo->u4PrivateData) ||
prAdapter->rWifiVar.fgCsaInProgress) {
DBGLOG(P2P, INFO, "skip due to CSA still in progress\n");
*pu2StatusCode = STATUS_CODE_UNSPECIFIED_FAILURE;
return FALSE;
}
if (bssGetClientCount(prAdapter, prP2pBssInfo)
>= P2P_MAXIMUM_CLIENT_COUNT
@ -10470,6 +10501,15 @@ p2pFuncNeedForceSleep(struct ADAPTER *prAdapter)
return TRUE;
}
u_int8_t
p2pFuncIsSapGoCsa(struct ADAPTER *prAdapter, uint8_t ucRoleIdx)
{
struct GLUE_INFO *prGlueInfo = prAdapter->prGlueInfo;
struct GL_P2P_INFO *prP2pInfo = prGlueInfo->prP2PInfo[ucRoleIdx];
return prP2pInfo->fgChannelSwitchReq;
}
void
p2pFunClearAllTxReq(struct ADAPTER *prAdapter,
struct P2P_MGMT_TX_REQ_INFO *prP2pMgmtTxInfo)

60
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/mgmt/rlm.c vendored
View File

@ -144,7 +144,7 @@ static void rlmFillVhtOpNotificationIE(struct ADAPTER *prAdapter,
static void rlmOpModeTxDoneHandler(struct ADAPTER *prAdapter,
struct MSDU_INFO *prMsduInfo,
uint8_t ucOpChangeType,
u_int8_t fgIsSuccess);
enum ENUM_TX_RESULT_CODE rTxDoneStatus);
static void rlmApGoOmiOpModeDoneHandler(struct ADAPTER *prAdapter,
struct MSDU_INFO *prMsduInfo);
static void rlmChangeOwnOpInfo(struct ADAPTER *prAdapter,
@ -8553,18 +8553,8 @@ uint32_t rlmNotifyVhtOpModeTxDone(struct ADAPTER *prAdapter,
struct MSDU_INFO *prMsduInfo,
enum ENUM_TX_RESULT_CODE rTxDoneStatus)
{
u_int8_t fgIsSuccess = FALSE;
do {
ASSERT((prAdapter != NULL) && (prMsduInfo != NULL));
if (rTxDoneStatus == TX_RESULT_SUCCESS)
fgIsSuccess = TRUE;
} while (FALSE);
rlmOpModeTxDoneHandler(prAdapter, prMsduInfo, OP_NOTIFY_TYPE_VHT_NSS_BW,
fgIsSuccess);
rTxDoneStatus);
return WLAN_STATUS_SUCCESS;
}
@ -8582,18 +8572,8 @@ uint32_t rlmNotifyOMIOpModeTxDone(struct ADAPTER *prAdapter,
struct MSDU_INFO *prMsduInfo,
enum ENUM_TX_RESULT_CODE rTxDoneStatus)
{
u_int8_t fgIsSuccess = FALSE;
do {
ASSERT((prAdapter != NULL) && (prMsduInfo != NULL));
if (rTxDoneStatus == TX_RESULT_SUCCESS)
fgIsSuccess = TRUE;
} while (FALSE);
rlmOpModeTxDoneHandler(prAdapter, prMsduInfo, OP_NOTIFY_TYPE_OMI_NSS_BW,
fgIsSuccess);
rTxDoneStatus);
return WLAN_STATUS_SUCCESS;
}
@ -8638,18 +8618,8 @@ uint32_t rlmSmPowerSaveTxDone(struct ADAPTER *prAdapter,
struct MSDU_INFO *prMsduInfo,
enum ENUM_TX_RESULT_CODE rTxDoneStatus)
{
u_int8_t fgIsSuccess = FALSE;
do {
ASSERT((prAdapter != NULL) && (prMsduInfo != NULL));
if (rTxDoneStatus == TX_RESULT_SUCCESS)
fgIsSuccess = TRUE;
} while (FALSE);
rlmOpModeTxDoneHandler(prAdapter, prMsduInfo, OP_NOTIFY_TYPE_HT_NSS,
fgIsSuccess);
rTxDoneStatus);
return WLAN_STATUS_SUCCESS;
}
@ -8667,18 +8637,8 @@ uint32_t rlmNotifyChannelWidthtTxDone(struct ADAPTER *prAdapter,
struct MSDU_INFO *prMsduInfo,
enum ENUM_TX_RESULT_CODE rTxDoneStatus)
{
u_int8_t fgIsSuccess = FALSE;
do {
ASSERT((prAdapter != NULL) && (prMsduInfo != NULL));
if (rTxDoneStatus == TX_RESULT_SUCCESS)
fgIsSuccess = TRUE;
} while (FALSE);
rlmOpModeTxDoneHandler(prAdapter, prMsduInfo, OP_NOTIFY_TYPE_HT_BW,
fgIsSuccess);
rTxDoneStatus);
return WLAN_STATUS_SUCCESS;
}
@ -8695,7 +8655,7 @@ uint32_t rlmNotifyChannelWidthtTxDone(struct ADAPTER *prAdapter,
static void rlmOpModeTxDoneHandler(struct ADAPTER *prAdapter,
struct MSDU_INFO *prMsduInfo,
uint8_t ucOpChangeType,
u_int8_t fgIsSuccess)
enum ENUM_TX_RESULT_CODE rTxDoneStatus)
{
uint32_t u4Status = WLAN_STATUS_SUCCESS;
struct BSS_INFO *prBssInfo = NULL;
@ -8703,6 +8663,7 @@ static void rlmOpModeTxDoneHandler(struct ADAPTER *prAdapter,
u_int8_t fgIsOpModeChangeSuccess = FALSE; /* OP change result */
uint8_t *pucCurrOpState = NULL;
uint8_t ucFailCnt = 0, i = 0;
u_int8_t fgIsSuccess = FALSE;
/* Sanity check */
ASSERT((prAdapter != NULL) && (prMsduInfo != NULL));
@ -8715,6 +8676,9 @@ static void rlmOpModeTxDoneHandler(struct ADAPTER *prAdapter,
if (!prStaRec)
return;
if (rTxDoneStatus == TX_RESULT_SUCCESS)
fgIsSuccess = TRUE;
DBGLOG(RLM, INFO,
"OP notification Tx done: BSS[%d] Type[%d] Status[%d] IsSuccess[%d]\n",
prBssInfo->ucBssIndex, ucOpChangeType,
@ -8766,6 +8730,10 @@ static void rlmOpModeTxDoneHandler(struct ADAPTER *prAdapter,
return;
}
} else {
/* Reduce useless retry to prevent long cnm req lock */
if (rTxDoneStatus == TX_RESULT_FLUSHED)
break;
/* Record rollback frame status to fail only */
if (prBssInfo->aucOpModeChangeState[ucOpChangeType]
== OP_NOTIFY_STATE_ROLLBACK) {

37
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/mgmt/rlm_domain.c vendored
View File

@ -5273,9 +5273,15 @@ rlmDomainBuildCmdByDefaultTable(struct ADAPTER *prAdapter,
uint16_t u2DefaultTableIndex)
{
uint16_t i, k;
#ifndef OPLUS_FEATURE_WIFI_PWR_LMT
//Add for distinguish country power limit at runtime.
struct COUNTRY_POWER_LIMIT_TABLE_DEFAULT *prPwrLimitSubBand =
&g_rRlmPowerLimitDefault[u2DefaultTableIndex];
#else
struct COUNTRY_POWER_LIMIT_TABLE_DEFAULT *prPwrLimitSubBand =
&g_prOplusCountryPwrLimitDefault[u2DefaultTableIndex];
#endif /*OPLUS_FEATURE_WIFI_PWR_LMT*/
struct CMD_CHANNEL_POWER_LIMIT *prPwrLimit = NULL;
struct CMD_CHANNEL_POWER_LIMIT_HE *prPwrLmtHE = NULL;
struct CMD_CHANNEL_POWER_LIMIT_HE_BW160 *prPwrLmtHEBW160 = NULL;
@ -5309,13 +5315,9 @@ rlmDomainBuildCmdByDefaultTable(struct ADAPTER *prAdapter,
"ucCountryPwrLimitCtrl setting[%x]",
prAdapter->rWifiVar.ucCountryPwrLimitCtrl);
#ifdef OPLUS_FEATURE_WIFI_PWR_LMT
#if (CFG_SUPPORT_PWR_LMT_EMI == 0)
prPwrLimitSubBand = &g_prOplusCountryPwrLimitDefault[u2DefaultTableIndex];
#endif
#endif /*OPLUS_FEATURE_WIFI_PWR_LMT*/
eType = prCmd->ucLimitType;
#ifndef OPLUS_FEATURE_WIFI_PWR_LMT
//Add for distinguish country power limit at runtime.
#if (CFG_SUPPORT_WIFI_6G_PWR_MODE == 1)
if (rlmDomainPwrLmt6GPwrModeGet(prAdapter) == PWR_MODE_6G_VLP) {
prPwrLimitSubBand =
@ -5325,6 +5327,7 @@ prPwrLimitSubBand = &g_prOplusCountryPwrLimitDefault[u2DefaultTableIndex];
&g_rRlmPowerLimitDefault_SP[u2DefaultTableIndex];
}
#endif
#endif /*OPLUS_FEATURE_WIFI_PWR_LMT*/
if (eType == PWR_LIMIT_TYPE_COMP_11AX)
prPwrLmtHE = &prCmd->u.rChPwrLimtHE[0];
@ -11312,8 +11315,11 @@ void rlmDomainSendPwrLimitCmd(struct ADAPTER *prAdapter)
uint32_t u4SetQueryInfoLen;
uint8_t bandedgeParam[4] = { 0, 0, 0, 0 };
uint8_t *pu1PwrLmtCountryCode;
#ifndef OPLUS_FEATURE_WIFI_PWR_LMT
struct COUNTRY_POWER_LIMIT_TABLE_DEFAULT *prPwrLmtDefaultTable =
g_rRlmPowerLimitDefault;
#endif /*OPLUS_FEATURE_WIFI_PWR_LMT*/
struct DOMAIN_INFO_ENTRY *prDomainInfo;
/* TODO : 5G band edge */
@ -11495,6 +11501,7 @@ void rlmDomainSendPwrLimitCmd(struct ADAPTER *prAdapter)
"Can't find any table index!\n");
goto err;
}
#ifndef OPLUS_FEATURE_WIFI_PWR_LMT
#if (CFG_SUPPORT_WIFI_6G_PWR_MODE == 1)
DBGLOG(RLM, TRACE, "Country 6G Power mode[%d]\n",
rlmDomainPwrLmt6GPwrModeGet(prAdapter));
@ -11506,24 +11513,16 @@ void rlmDomainSendPwrLimitCmd(struct ADAPTER *prAdapter)
pu1PwrLmtCountryCode = &prPwrLmtDefaultTable[u2DefaultTableIndex]
.aucCountryCode[0];
#ifdef OPLUS_FEATURE_WIFI_PWR_LMT
#if (CFG_SUPPORT_PWR_LMT_EMI == 0)
WLAN_GET_FIELD_BE16(&g_prOplusCountryPwrLimitDefault
[u2DefaultTableIndex]
.aucCountryCode[0],
&prCmd->u2CountryCode);
WLAN_GET_FIELD_BE16(&g_prOplusCountryPwrLimitDefault
[u2DefaultTableIndex]
.aucCountryCode[0],
&prCmdHE->u2CountryCode);
#endif
#else
pu1PwrLmtCountryCode = &g_prOplusCountryPwrLimitDefault[u2DefaultTableIndex]
.aucCountryCode[0];
#endif /*OPLUS_FEATURE_WIFI_PWR_LMT*/
WLAN_GET_FIELD_BE16(pu1PwrLmtCountryCode,
&prCmd->u2CountryCode);
WLAN_GET_FIELD_BE16(pu1PwrLmtCountryCode,
&prCmdHE->u2CountryCode);
#endif /*OPLUS_FEATURE_WIFI_PWR_LMT*/
#if (CFG_SUPPORT_PWR_LIMIT_EHT == 1)
WLAN_GET_FIELD_BE16(pu1PwrLmtCountryCode,

3
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/nic/nic_rate.c vendored
View File

@ -386,7 +386,8 @@ nicRateCode2DataRate(
u4PhyRateIn100Kbps = (nicGetHwRateByPhyRate(
ucPhyRate & BITS(0, 3))) * 5;
} else {
ASSERT(FALSE);
DBGLOG(INIT, ERROR, "Invalid TxMode = %x\n", u2TxMode);
return 0;
}
return u4PhyRateIn100Kbps;
}

3
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/nic/nic_tx.c vendored
View File

@ -4777,7 +4777,8 @@ void nicTxSetPktLowestFixedRate(struct ADAPTER *prAdapter,
u4CurrentPhyRate = nicRateCode2PhyRate(u2RateCode,
FIX_BW_NO_FIXED, MAC_GI_NORMAL, AR_SS_NULL);
if (prBssInfo->u4CoexPhyRateLimit > u4CurrentPhyRate) {
if (u4CurrentPhyRate &&
prBssInfo->u4CoexPhyRateLimit > u4CurrentPhyRate) {
nicGetRateIndexFromRateSetWithLimit(
u2OperationalRateSet,
prBssInfo->u4CoexPhyRateLimit,

205
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/os/linux/gl_kal.c vendored
View File

@ -2143,6 +2143,21 @@ void kal_gro_flush(struct ADAPTER *prAdapter)
GET_CURRENT_SYSTIME(&prGlueInfo->tmGROFlushTimeout);
}
#endif
void kal_netif_rx(struct GLUE_INFO *prGlueInfo, struct sk_buff *prSkb)
{
#if KERNEL_VERSION(5, 18, 0) <= LINUX_VERSION_CODE
netif_rx(prSkb);
#else
if (!in_interrupt())
netif_rx_ni(prSkb);
else
netif_rx(prSkb);
#endif
RX_INC_CNT(&prGlueInfo->prAdapter->rRxCtrl,
RX_DATA_INDICATION_END_COUNT);
}
/*----------------------------------------------------------------------------*/
/*!
* \brief To indicate one received packets is available for higher
@ -2315,16 +2330,34 @@ uint32_t kalRxIndicateOnePkt(struct GLUE_INFO
spin_unlock_bh(&prGlueInfo->napi_spinlock);
preempt_enable();
} else {
skb_queue_tail(&prGlueInfo->rRxNapiSkbQ, prSkb);
RX_INC_CNT(&prGlueInfo->prAdapter->rRxCtrl,
RX_NAPI_SCHEDULE_COUNT);
GLUE_SET_REF_CNT(1, prGlueInfo->fgNapiScheduled);
if (prGlueInfo->fgNapiReady)
kal_napi_schedule(&prGlueInfo->napi);
else
DBGLOG(RX, WARN,
"Skip napi schedule, NapiReady:%u\n",
prGlueInfo->fgNapiReady);
if (prGlueInfo->fgNapiReady &&
!prGlueInfo->fgNapiScheduleTimeout) {
skb_queue_tail(&prGlueInfo->rRxNapiSkbQ, prSkb);
if (kal_napi_schedule(&prGlueInfo->napi)) {
RX_INC_CNT(
&prGlueInfo->prAdapter->rRxCtrl,
RX_NAPI_SCHEDULE_COUNT);
}
} else {
RX_INC_CNT(
&prGlueInfo->prAdapter->rRxCtrl,
RX_NAPI_SCHEDULE_FAIL_COUNT);
DBGLOG(RX, TRACE,
"Skip napi schedule fail, NapiReady:%u NapiScheduleTimeout:%u\n",
prGlueInfo->fgNapiReady,
prGlueInfo->fgNapiScheduleTimeout);
if (skb_queue_len(&prGlueInfo->rRxNapiSkbQ)) {
while ((prSkb = skb_dequeue(
&prGlueInfo->rRxNapiSkbQ))
!= NULL) {
kal_netif_rx(prGlueInfo,
prSkb);
}
} else {
kal_netif_rx(prGlueInfo, prSkb);
}
}
}
#else /* CFG_SUPPORT_RX_NAPI */
/* GRO receive function can't be interrupt so it need to
@ -2347,16 +2380,8 @@ skip_gro:
#endif /* CFG_SUPPORT_SKIP_RX_GRO_FOR_TC */
#endif /* CFG_SUPPORT_RX_GRO */
#if KERNEL_VERSION(5, 18, 0) <= LINUX_VERSION_CODE
netif_rx(prSkb);
#else
if (!in_interrupt())
netif_rx_ni(prSkb);
else
netif_rx(prSkb);
#endif
RX_INC_CNT(&prGlueInfo->prAdapter->rRxCtrl,
RX_DATA_INDICATION_END_COUNT);
kal_netif_rx(prGlueInfo, prSkb);
return WLAN_STATUS_SUCCESS;
}
@ -11727,9 +11752,9 @@ static uint32_t kalPerMonUpdate(struct ADAPTER *prAdapter)
#endif /* CFG_QUEUE_RX_IF_CONN_NOT_READY */
#if CFG_SUPPORT_RX_GRO
#define NAPI_TEMPLATE "NAPI[%lu,%lu,%u,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%u] "
#define NAPI_TEMPLATE "NAPI[%lu,%lu,0x%03x,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%u] "
#else
#define NAPI_TEMPLATE "NAPI[%lu,%lu,%u,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu] "
#define NAPI_TEMPLATE "NAPI[%lu,%lu,0x%03x,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu,%lu] "
#endif
#if CFG_NAPI_DELAY
@ -11759,9 +11784,10 @@ static uint32_t kalPerMonUpdate(struct ADAPTER *prAdapter)
head3,
RX_GET_CNT(&prAdapter->rRxCtrl, RX_INTR_COUNT),
RX_GET_CNT(&prAdapter->rRxCtrl, RX_TASKLET_COUNT),
glue->fgNapiScheduled,
glue->napi.state,
RX_GET_CNT(&prAdapter->rRxCtrl, RX_NAPI_WORK_COUNT),
RX_GET_CNT(&prAdapter->rRxCtrl, RX_NAPI_SCHEDULE_COUNT),
RX_GET_CNT(&prAdapter->rRxCtrl, RX_NAPI_SCHEDULE_FAIL_COUNT),
RX_GET_CNT(&prAdapter->rRxCtrl, RX_NAPI_LEGACY_SCHED_COUNT),
RX_GET_CNT(&prAdapter->rRxCtrl, RX_NAPI_POLL_COUNT),
RX_GET_CNT(&prAdapter->rRxCtrl, RX_NAPI_POLL_END_COUNT),
@ -14993,16 +15019,54 @@ void kal_napi_complete_done(struct napi_struct *n, int work_done)
#endif /* KERNEL_VERSION(3, 19, 0) */
}
void kal_napi_schedule(struct napi_struct *n)
uint8_t kal_napi_schedule(struct napi_struct *n)
{
if (!n)
return;
return FALSE;
#if KERNEL_VERSION(4, 0, 0) <= CFG80211_VERSION_CODE
if (in_interrupt())
if (in_interrupt()) {
napi_schedule_irqoff(n);
else
return TRUE;
}
#endif /* KERNEL_VERSION(4, 0, 0) */
napi_schedule(n);
if (napi_schedule_prep(n)) {
__napi_schedule(n);
return TRUE;
}
return FALSE;
}
void kal_napi_synchronize(struct napi_struct *n)
{
static OS_SYSTIME now, last;
uint32_t u4LastState;
GET_CURRENT_SYSTIME(&last);
if (IS_ENABLED(CONFIG_SMP))
while (test_bit(NAPI_STATE_SCHED, &n->state)) {
msleep(1);
u4LastState = n->state;
GET_CURRENT_SYSTIME(&now);
if (CHECK_FOR_TIMEOUT(now, last,
MSEC_TO_SYSTIME(3 * MSEC_PER_SEC)) &&
test_bit(NAPI_STATE_SCHED, &n->state)) {
clear_bit(NAPI_STATE_SCHED, &n->state);
clear_bit(NAPIF_STATE_NPSVC, &n->state);
DBGLOG(RX, WARN,
"RX NAPI synchronize timeout:%lu, reset state:0x%03x->0x%03x,\n",
(last - now) ?
((last-now) / MSEC_PER_SEC) : 0,
u4LastState,
n->state);
}
}
else
barrier();
}
#if CFG_SUPPORT_RX_GRO
@ -15121,11 +15185,11 @@ static inline void __kalNapiSchedule(struct ADAPTER *prAdapter)
}
prRxCtrl = &prAdapter->rRxCtrl;
RX_INC_CNT(prRxCtrl, RX_NAPI_SCHEDULE_COUNT);
GLUE_SET_REF_CNT(1, prGlueInfo->fgNapiScheduled);
kal_napi_schedule(prGlueInfo->prRxDirectNapi);
if (kal_napi_schedule(prGlueInfo->prRxDirectNapi)) {
RX_INC_CNT(prRxCtrl, RX_NAPI_SCHEDULE_COUNT);
} else {
RX_INC_CNT(prRxCtrl, RX_NAPI_SCHEDULE_FAIL_COUNT);
}
}
static inline void _kalNapiSchedule(struct ADAPTER *prAdapter)
@ -15140,40 +15204,55 @@ static inline void _kalNapiSchedule(struct ADAPTER *prAdapter)
#endif /* CFG_SUPPORT_RX_NAPI_WORK */
}
static void kalNapiScheduleCheck(struct GLUE_INFO *pr)
static void kalNapiScheduleCheck(struct GLUE_INFO *prGlueInfo)
{
struct WIFI_VAR *prWifiVar = &prGlueInfo->prAdapter->rWifiVar;
static OS_SYSTIME now, last;
uint32_t u4ScheduleTimeout;
uint32_t u4ScheduleCnt, u4NapiPollCnt;
uint32_t u4NapiPollCnt;
GET_BOOT_SYSTIME(&now);
GET_CURRENT_SYSTIME(&now);
u4ScheduleCnt =
RX_GET_CNT(&pr->prAdapter->rRxCtrl, RX_NAPI_SCHEDULE_COUNT);
u4NapiPollCnt =
RX_GET_CNT(&pr->prAdapter->rRxCtrl, RX_NAPI_POLL_COUNT);
u4NapiPollCnt = RX_GET_CNT(&prGlueInfo->prAdapter->rRxCtrl,
RX_NAPI_POLL_COUNT);
if (!pr->fgNapiScheduled) {
pr->u4LastScheduleCnt = u4ScheduleCnt;
pr->u4LastNapiPollCnt = u4NapiPollCnt;
if ((KAL_GET_FIFO_CNT(prGlueInfo) == 0 &&
skb_queue_len(&prGlueInfo->rRxNapiSkbQ) == 0) ||
prGlueInfo->u4LastNapiPollCnt != u4NapiPollCnt) {
prGlueInfo->u4LastNapiPollCnt = u4NapiPollCnt;
last = 0;
} else if ((KAL_GET_FIFO_CNT(prGlueInfo) != 0 ||
skb_queue_len(&prGlueInfo->rRxNapiSkbQ) != 0)&&
u4NapiPollCnt == prGlueInfo->u4LastNapiPollCnt &&
last == 0) {
last = now;
return;
}
if (pr->u4LastNapiPollCnt != 0 &&
u4ScheduleCnt > pr->u4LastScheduleCnt &&
u4NapiPollCnt == pr->u4LastNapiPollCnt) {
u4ScheduleTimeout =
pr->prAdapter->rWifiVar.u4NapiScheduleTimeout
* MSEC_PER_SEC;
if (CHECK_FOR_TIMEOUT(now, last,
MSEC_TO_SYSTIME(u4ScheduleTimeout)))
kalSendAeeWarning("Napi Schedule Timeout",
"Napi Schedule Timeout\n");
DBGLOG(INIT, WARN,
"FIFOCnt[%u] NapiSkbQ[%u] NapiState[%u] NapiPollCnt[%u/%u] Timestamp[%lu]\n",
KAL_GET_FIFO_CNT(prGlueInfo),
skb_queue_len(&prGlueInfo->rRxNapiSkbQ),
prGlueInfo->napi.state,
u4NapiPollCnt, prGlueInfo->u4LastNapiPollCnt,
last);
} else {
pr->u4LastScheduleCnt = u4ScheduleCnt;
pr->u4LastNapiPollCnt = u4NapiPollCnt;
last = now;
u4ScheduleTimeout = prWifiVar->u4NapiScheduleTimeout
* MSEC_PER_SEC;
if (CHECK_FOR_TIMEOUT(now, last,
MSEC_TO_SYSTIME(u4ScheduleTimeout))) {
DBGLOG(INIT, WARN,
"FIFOCnt[%u] NapiSkbQ[%u] NapiState[%u] NapiPollCnt[%u/%u] Timestamp[%lu/%lu]\n",
KAL_GET_FIFO_CNT(prGlueInfo),
skb_queue_len(&prGlueInfo->rRxNapiSkbQ),
prGlueInfo->napi.state,
u4NapiPollCnt, prGlueInfo->u4LastNapiPollCnt,
now, last);
GLUE_SET_REF_CNT(1, prGlueInfo->fgNapiScheduleTimeout);
if (prWifiVar->fgNapiScheduleAeeEn)
kalSendAeeWarning("Napi Schedule Timeout",
"Napi Schedule Timeout\n");
}
}
}
@ -15473,7 +15552,9 @@ int kalNapiPoll(struct napi_struct *napi, int budget)
/* follow timeout rule in net_rx_action() */
const unsigned long ulTimeLimit = jiffies + 2;
#endif
GLUE_SET_REF_CNT(0, prGlueInfo->fgNapiScheduled);
GLUE_SET_REF_CNT(0, prGlueInfo->fgNapiScheduleTimeout);
RX_INC_CNT(&prGlueInfo->prAdapter->rRxCtrl, RX_NAPI_POLL_COUNT);
if (HAL_IS_RX_DIRECT(prGlueInfo->prAdapter)) {
@ -15566,7 +15647,7 @@ next_try:
kal_napi_complete_done(napi, work_done);
if (skb_queue_len(prRxNapiSkbQ) && prGlueInfo->fgNapiReady) {
RX_INC_CNT(&prAdapter->rRxCtrl, RX_NAPI_LEGACY_SCHED_COUNT);
napi_schedule(napi);
__napi_schedule(napi);
}
RX_INC_CNT(&prGlueInfo->prAdapter->rRxCtrl, RX_NAPI_POLL_END_COUNT);
@ -15588,14 +15669,13 @@ uint8_t kalNapiEnable(struct GLUE_INFO *prGlueInfo)
uint8_t kalNapiDisable(struct GLUE_INFO *prGlueInfo)
{
DBGLOG(RX, INFO, "RX NAPI disable ongoing\n");
GLUE_SET_REF_CNT(0, prGlueInfo->fgNapiScheduled);
prGlueInfo->fgNapiReady = FALSE;
#if CFG_NAPI_DELAY
kalNapiDelayTimerUninit(prGlueInfo);
#endif /* CFG_NAPI_DELAY */
napi_synchronize(&prGlueInfo->napi);
kal_napi_synchronize(&prGlueInfo->napi);
napi_disable(&prGlueInfo->napi);
if (skb_queue_len(&prGlueInfo->rRxNapiSkbQ)) {
struct sk_buff *skb;
@ -15607,6 +15687,7 @@ uint8_t kalNapiDisable(struct GLUE_INFO *prGlueInfo)
!= NULL)
kfree_skb(skb);
}
DBGLOG(RX, TRACE, "RX NAPI disabled\n");
return 0;
}

27
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/os/linux/gl_p2p_cfg80211.c vendored
View File

@ -3050,6 +3050,7 @@ int _mtk_p2p_cfg80211_mgmt_tx(struct wiphy *wiphy,
uint8_t ucRoleIdx = 0, ucBssIdx = 0;
int32_t i4Rslt = -EINVAL;
struct net_device *dev = NULL;
enum ENUM_P2P_CONNECT_STATE eCNNState;
do {
if ((wiphy == NULL) || (wdev == NULL) ||
@ -3137,10 +3138,6 @@ int _mtk_p2p_cfg80211_mgmt_tx(struct wiphy *wiphy,
break;
}
prMsgTxReq->u8Cookie = *cookie;
prMsgTxReq->rMsgHdr.eMsgId = MID_MNY_P2P_MGMT_TX;
prMsgTxReq->ucBssIdx = ucBssIdx;
pucFrameBuf =
(uint8_t *)
((unsigned long) prMgmtFrame->prPacket
@ -3158,6 +3155,19 @@ int _mtk_p2p_cfg80211_mgmt_tx(struct wiphy *wiphy,
prMgmtFrame->u2FrameLength = len;
eCNNState = p2pFuncTagMgmtFrame(prMsgTxReq->prMgmtMsduInfo,
*cookie);
prMsgTxReq->u8Cookie = *cookie;
prMsgTxReq->rMsgHdr.eMsgId = MID_MNY_P2P_MGMT_TX;
if (eCNNState == P2P_CNN_INVITATION_REQ) {
DBGLOG(P2P, INFO, "INVITATION_REQ change bssIdx\n");
prMsgTxReq->ucBssIdx =
prGlueInfo->prAdapter->ucP2PDevBssIdx;
} else
prMsgTxReq->ucBssIdx = ucBssIdx;
#define TEMP_LOG_TEMPLATE "[%s] bssIdx: %d, band: %d, chan: %d, " \
"offchan: %d, wait: %d, len: %d, no_cck: %d, " \
"dont_wait_for_ack: %d, link_id: %d, cookie: 0x%llx\n"
@ -3241,6 +3251,7 @@ int mtk_p2p_cfg80211_mgmt_tx_cancel_wait(struct wiphy *wiphy,
uint8_t ucRetry = 0;
struct MSG_CANCEL_TX_WAIT_REQUEST *prMsgCancelTxWait =
(struct MSG_CANCEL_TX_WAIT_REQUEST *) NULL;
struct P2P_PENDING_MGMT_INFO *prPendingMgmtInfo = NULL;
do {
ASSERT(wiphy);
@ -3262,6 +3273,14 @@ int mtk_p2p_cfg80211_mgmt_tx_cancel_wait(struct wiphy *wiphy,
}
}
if (p2pFuncGetBssIdxByCookie(prGlueInfo->prAdapter,
ucRoleIdx,
&prPendingMgmtInfo,
cookie) &&
prPendingMgmtInfo &&
IS_BSS_INDEX_VALID(prPendingMgmtInfo->ucBssIdx))
ucBssIdx = prPendingMgmtInfo->ucBssIdx;
DBGLOG(P2P, INFO, "bssIdx: %d, cookie: 0x%llx\n",
ucBssIdx,
cookie);

23
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/os/linux/hif/common/kal_pdma.c vendored
View File

@ -3014,10 +3014,12 @@ end:
}
#endif /* CFG_SUPPORT_PDMA_SCATTER */
void kalCheckRxDmadAddr(struct RTMP_DMACB *pRxCell,
static u_int8_t kalCheckRxDmadAddr(struct GLUE_INFO *prGlueInfo,
struct RTMP_DMACB *pRxCell,
struct RXD_STRUCT *pRxD, struct RTMP_DMABUF *prDmaBuf)
{
uint64_t u8Addr = 0;
struct ADAPTER *prAdapter = NULL;
u8Addr = pRxD->SDPtr0;
#ifdef CONFIG_PHYS_ADDR_T_64BIT
@ -3025,12 +3027,17 @@ void kalCheckRxDmadAddr(struct RTMP_DMACB *pRxCell,
DMA_BITS_OFFSET;
#endif
if (u8Addr != (uint64_t)prDmaBuf->AllocPa) {
DBGLOG(HAL, ERROR, "Dump RXDMAD PA[0x%llx]!=[0x%llx]:\n",
DBGLOG(HAL, ERROR,
"Dump RXDMAD PA[0x%llx]!=[0x%llx]: Trigger SER\n",
u8Addr, (uint64_t)prDmaBuf->AllocPa);
DBGLOG_MEM32(RX, INFO, pRxCell->AllocVa,
sizeof(struct RXD_STRUCT));
ASSERT(0);
prAdapter = prGlueInfo->prAdapter;
prAdapter->u4HifChkFlag |= HIF_DRV_SER;
kalSetHifDbgEvent(prGlueInfo);
return FALSE;
}
return TRUE;
}
bool kalDevReadData(struct GLUE_INFO *prGlueInfo, uint16_t u2Port,
@ -3119,7 +3126,11 @@ bool kalDevReadData(struct GLUE_INFO *prGlueInfo, uint16_t u2Port,
prDmaBuf = &pRxCell->DmaBuf;
kalCheckRxDmadAddr(pRxCell, pRxD, prDmaBuf);
if (kalCheckRxDmadAddr(prGlueInfo, pRxCell, pRxD, prDmaBuf)
== FALSE) {
fgRet = false;
goto skip;
}
if (prMemOps->copyRxData &&
!prMemOps->copyRxData(prHifInfo, pRxCell, prDmaBuf, prSwRfb)) {

1
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/os/linux/hif/pcie/include/hif.h vendored
View File

@ -619,6 +619,7 @@ struct BUS_INFO {
u_int8_t (*checkPortForRxEventFromPse)(struct ADAPTER *prAdapter,
uint8_t u2Port);
#endif
struct timespec64 rHifIntTs;
uint32_t u4EnHifIntTs;
uint32_t u4HifIntTsCnt;

3
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/os/linux/include/gl_kal.h vendored
View File

@ -2531,13 +2531,12 @@ kalChannelFormatSwitch(struct cfg80211_chan_def *channel_def,
struct RF_CHANNEL_INFO *prRfChnlInfo);
void kal_napi_complete_done(struct napi_struct *n, int work_done);
void kal_napi_schedule(struct napi_struct *n);
uint8_t kal_napi_schedule(struct napi_struct *n);
#if CFG_SUPPORT_RX_GRO
uint8_t kalRxGroInit(struct net_device *prDev);
uint32_t kal_is_skb_gro(struct ADAPTER *prAdapter, uint8_t ucBssIdx);
void kal_gro_flush(struct ADAPTER *prAdapter);
void kal_napi_schedule(struct napi_struct *n);
int kalNapiPoll(struct napi_struct *napi, int budget);
uint8_t kalNapiInit(struct GLUE_INFO *prGlueInfo);
uint8_t kalNapiUninit(struct GLUE_INFO *prGlueInfo);

3
vendor/mediatek/kernel_modules/connectivity/wlan/core/gen4m/os/linux/include/gl_os.h vendored
View File

@ -1053,10 +1053,9 @@ struct GLUE_INFO {
struct napi_struct *prRxDirectNapi;
struct kfifo rRxKfifoQ;
u_int8_t fgNapiReady;
u_int8_t fgNapiScheduleTimeout;
uint8_t *prRxKfifoBuf;
uint32_t u4RxKfifoBufLen;
u_int8_t fgNapiScheduled;
uint32_t u4LastScheduleCnt;
uint32_t u4LastNapiPollCnt;
#if CFG_NAPI_DELAY
struct hrtimer rNapiDelayTimer;

5
vendor/mediatek/kernel_modules/gpu/gpu_mali/mali_avalon/mali-r49p1/drivers/gpu/arm/midgard/mali_kbase_mem_migrate.c vendored
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
/*
*
* (C) COPYRIGHT 2022-2024 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2022-2025 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@ -157,9 +157,8 @@ static void kbase_free_pages_worker(struct work_struct *work)
__ClearPageMovable(p);
page_md->status = PAGE_MOVABLE_CLEAR(page_md->status);
}
unlock_page(p);
kbase_free_page_metadata(kbdev, p, &group_id);
unlock_page(p);
kbdev->mgm_dev->ops.mgm_free_page(kbdev->mgm_dev, group_id, p, 0);
}
}

6
vendor/mediatek/kernel_modules/gpu/gpu_mali/mali_avalon/mali-r49p1/drivers/gpu/arm/midgard/mmu/mali_kbase_mmu.c vendored
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
/*
*
* (C) COPYRIGHT 2010-2024 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2010-2025 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@ -4635,6 +4635,8 @@ static void kbase_mmu_mark_non_movable(struct kbase_device *const kbdev, struct
if (!kbase_is_page_migration_enabled())
return;
lock_page(page);
/* Composite large-page is excluded from migration, trigger a warn if a development
* wrongly leads to it.
*/
@ -4650,7 +4652,9 @@ static void kbase_mmu_mark_non_movable(struct kbase_device *const kbdev, struct
if (IS_PAGE_MOVABLE(page_md->status))
page_md->status = PAGE_MOVABLE_CLEAR(page_md->status);
__ClearPageMovable(page);
spin_unlock(&page_md->migrate_lock);
unlock_page(page);
}
int kbase_mmu_init(struct kbase_device *const kbdev, struct kbase_mmu_table *const mmut,

21
vendor/mediatek/kernel_modules/gpu/gpu_mali/mali_avalon/mali-r49p1/drivers/gpu/arm/midgard/platform/mt6991/mali_kbase_config_mt6991.c vendored
View File

@ -452,19 +452,14 @@ static void pm_callback_runtime_gpu_active(struct kbase_device *kbdev)
mtk_common_ged_dvfs_write_sysram_last_commit_top_idx();
mtk_common_ged_dvfs_write_sysram_last_commit_dual();
if (pm_runtime_status_suspended(kbdev->dev)) {
error = pm_runtime_get_sync(kbdev->dev);
KBASE_PLATFORM_LOGD("pm_runtime_get_sync returned %d", error);
} else {
/* Call the async version here, otherwise there could be
* a deadlock if the runtime suspend operation is ongoing.
* Caller would have taken the kbdev->pm.lock and/or the
* scheduler lock, and the runtime suspend callback function
* will also try to acquire the same lock(s).
*/
error = pm_runtime_get(kbdev->dev);
KBASE_PLATFORM_LOGD("pm_runtime_get returned %d", error);
}
/* Call the async version here, otherwise there could be
* a deadlock if the runtime suspend operation is ongoing.
* Caller would have taken the kbdev->pm.lock and/or the
* scheduler lock, and the runtime suspend callback function
* will also try to acquire the same lock(s).
*/
error = pm_runtime_get(kbdev->dev);
KBASE_PLATFORM_LOGD("pm_runtime_get returned %d", error);
kbdev->pm.runtime_active = true;

2
vendor/mediatek/kernel_modules/mtkcam/cam_cal/src_v4l2/custom/cam_cal_config.c vendored
View File

@ -1137,7 +1137,7 @@ EXPORT_SYMBOL(read_cam_cal);
void custom_eeprom_read(bool *is_valid, void *d_data)
{
*is_valid = (preload_ois.valid == 0x01) ? true : false;
if (d_data)
if (d_data && (*is_valid))
memcpy(d_data, preload_ois.ois_table, sizeof(preload_ois.ois_table));
return;
}

29
vendor/mediatek/kernel_modules/mtkcam/camsys/isp8/cam/mtk_cam-job.c vendored
View File

@ -70,6 +70,19 @@ static inline bool check_qof_support(struct mtk_cam_job *job)
return (GET_PLAT_HW(qof_support) && !disable_qof && !job->enable_hsf_raw && !is_ois_compensation(job));
}
#ifdef OPLUS_FEATURE_CAMERA_COMMON
/* wa: for performace, dc mode work buffer increasing */
static inline void wa_for_srt(struct mtk_cam_job *job)
{
if (!is_dc_mode(job)) {
return;
}
if (is_buffer_increase(job)) {
job->scq_period = job->scq_period * 10;
}
}
#endif
static struct mtk_raw_request_data *req_get_raw_data(struct mtk_cam_ctx *ctx,
struct mtk_cam_request *req);
static bool is_sensor_mode_update(struct mtk_cam_job *job);
@ -1277,11 +1290,11 @@ _stream_on(struct mtk_cam_job *job, bool on)
/* ois compensation */
#ifndef OPLUS_FEATURE_CAMERA_COMMON
if (is_ois_compensation(job))
mtk_cam_tuning_init(&job->tuning_param);
mtk_cam_tuning_init(job);
#else /*OPLUS_FEATURE_CAMERA_COMMON*/
if (is_ois_compensation(job)) {
ctx->is_ois_compensation = 1;
mtk_cam_tuning_init(&job->tuning_param);
mtk_cam_tuning_init(job);
}
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
@ -3048,6 +3061,11 @@ _job_pack_otf_stagger(struct mtk_cam_job *job,
/* check if slave raw need to init or uninit */
job_raw_change_hw_init(job);
}
#ifdef OPLUS_FEATURE_CAMERA_COMMON
wa_for_srt(job);
#endif
job->do_ipi_config = false;
if (check_if_need_configure(ctx->configured, job->seamless_switch,
job->raw_switch, job->raw_change)) {
@ -3329,6 +3347,11 @@ _job_pack_normal(struct mtk_cam_job *job,
/* check if slave/new raw need to uninit or init */
job_raw_change_hw_init(job);
}
#ifdef OPLUS_FEATURE_CAMERA_COMMON
wa_for_srt(job);
#endif
job->do_ipi_config = false;
if (check_if_need_configure(ctx->configured,
job->seamless_switch,
@ -4413,7 +4436,7 @@ _common_seamless_after_frame_done(struct mtk_cam_job *job)
job, job->raw_change_uninit_engine);
if (is_ois_comp)
mtk_cam_tuning_init(&job->tuning_param);
mtk_cam_tuning_init(job);
lock_done_ctrl_enable(raw_dev, is_ois_comp);
stream_on(raw_dev, 1, false);

11
vendor/mediatek/kernel_modules/mtkcam/camsys/isp8/cam/mtk_cam-job_utils.c vendored Normal file → Executable file
View File

@ -2007,7 +2007,18 @@ bool is_ois_compensation(struct mtk_cam_job *job)
return res_raw_ois_compensation(&res->raw_res);
}
#ifdef OPLUS_FEATURE_CAMERA_COMMON
bool is_buffer_increase(struct mtk_cam_job *job)
{
struct mtk_cam_resource_v2 *res;
res = _get_job_res(job);
if (!res)
return false;
return res_raw_is_buffer_increase(&res->raw_res);
}
#endif
bool is_rgbw(struct mtk_cam_job *job)
{
return scen_is_rgbw(&job->job_scen);

3
vendor/mediatek/kernel_modules/mtkcam/camsys/isp8/cam/mtk_cam-job_utils.h vendored Normal file → Executable file
View File

@ -151,6 +151,9 @@ int get_exp_order(struct mtk_cam_scen *scen);
bool is_vhdr(struct mtk_cam_job *job);
bool is_dc_mode(struct mtk_cam_job *job);
bool is_ois_compensation(struct mtk_cam_job *job);
#ifdef OPLUS_FEATURE_CAMERA_COMMON
bool is_buffer_increase(struct mtk_cam_job *job);
#endif
bool is_sv_pure_raw(struct mtk_cam_job *job);
bool is_offline_timeshare(struct mtk_cam_job *job);
bool is_rgbw(struct mtk_cam_job *job);

7
vendor/mediatek/kernel_modules/mtkcam/camsys/isp8/cam/mtk_cam-raw_ctrl.h vendored Normal file → Executable file
View File

@ -33,6 +33,13 @@ bool res_raw_ois_compensation(const struct mtk_cam_resource_raw_v2 *res_raw)
return res_raw->ois_compensation == 1;
}
#ifdef OPLUS_FEATURE_CAMERA_COMMON
static inline
bool res_raw_is_buffer_increase(const struct mtk_cam_resource_raw_v2 *res_raw)
{
return res_raw->buffer_increase == 1;
}
#endif
static inline bool scen_is_normal(const struct mtk_cam_scen *scen)
{
return scen->id == MTK_CAM_SCEN_NORMAL ||

19
vendor/mediatek/kernel_modules/mtkcam/camsys/isp8/cam/mtk_cam-raw_pipeline.c vendored
View File

@ -311,10 +311,29 @@ mtk_cam_resource_update_work_buf(struct mtk_cam_resource_v2 *user_ctrl)
exp_num = (scen->scen.normal.exp_num == 0) ?
1 : scen->scen.normal.exp_num;
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
#ifdef OPLUS_FEATURE_CAMERA_COMMON
/* wa: for performace, dc mode work buffer increasing */
if (r->buffer_increase == 1) {
buf_require = res_raw_is_dc_mode(r) ? exp_num * 2 : exp_num - 1;
buf_require = !!(scen->scen.normal.w_chn_supported) ?
buf_require * 2 : buf_require;
if (res_raw_is_dc_mode(r))
buf_require = buf_require + (r->ois_compensation ? exp_num : 0);
else
buf_require = buf_require * (r->ois_compensation ? 2 : 1);
} else {
buf_require = res_raw_is_dc_mode(r) ? exp_num : exp_num - 1;
buf_require = !!(scen->scen.normal.w_chn_supported) ?
buf_require * 2 : buf_require;
buf_require = buf_require * (r->ois_compensation ? 2 : 1);
}
#else
buf_require = res_raw_is_dc_mode(r) ? exp_num : exp_num - 1;
buf_require = !!(scen->scen.normal.w_chn_supported) ?
buf_require * 2 : buf_require;
buf_require = buf_require * (r->ois_compensation ? 2 : 1);
#endif
break;
case MTK_CAM_SCEN_MSTREAM:
buf_require = res_raw_is_dc_mode(r) ? 2 : 1;

50
vendor/mediatek/kernel_modules/mtkcam/camsys/isp8/cam/mtk_cam-tuning.c vendored
View File

@ -5,10 +5,15 @@
#include "mtk_cam.h"
// This macro needs to be consistent with the macro definition in the following file
// vendor/oplus/hardware/camera/mtkcam/mtkcam-custom/aaa/aaa/lsc/OplusShadingUtil.cpp
#define OTP_SIZE 2340
#define OTP_DATA_INDEX_NUM (9)
#define OTP_DATA_TABLE_NUM (130)
extern void custom_eeprom_read(bool *is_valid, void *d_data);
static bool do_set_otp_once;
static unsigned char ois_otp[OTP_SIZE];
static unsigned char swap_ois_otp[OTP_SIZE];
/*
@ -1439,6 +1444,36 @@ void oplus_cam_copy_res(int *pInBuf, struct mtk_cam_tuning *param)
}
}
void oplus_get_sensor_mirror_type(struct mtk_cam_job *job, u8* mirror)
{
if (job &&
job->sensor &&
job->sensor->ops &&
job->sensor->ops->core &&
job->sensor->ops->core->command) {
job->sensor->ops->core->command(job->sensor,
V4L2_CMD_GET_SENSOR_MIRROR_TYPE,
mirror);
}
}
void oplus_swap_otp_data(unsigned char* ori_otp_data, unsigned char* swap_otp_data)
{
int i;
int j;
for (i = 0; i < OTP_DATA_INDEX_NUM; i++) {
swap_otp_data[i * (OTP_DATA_TABLE_NUM * 2)] = ori_otp_data[i * (OTP_DATA_TABLE_NUM * 2)];
swap_otp_data[i * (OTP_DATA_TABLE_NUM * 2) + 1] = ori_otp_data[i * (OTP_DATA_TABLE_NUM * 2) + 1];
for (j = 1; j < OTP_DATA_TABLE_NUM; j++) {
swap_otp_data[i * (OTP_DATA_TABLE_NUM * 2) + j * 2] =
ori_otp_data[i * (OTP_DATA_TABLE_NUM * 2) + (OTP_DATA_TABLE_NUM - j) * 2];
swap_otp_data[i * (OTP_DATA_TABLE_NUM * 2) + j * 2 + 1] =
ori_otp_data[i * (OTP_DATA_TABLE_NUM * 2) + (OTP_DATA_TABLE_NUM - j) * 2 + 1];
}
}
pr_info("%s: \n", __func__);
}
/*
* oplus's part: end
*/
@ -1447,8 +1482,9 @@ void mtk_cam_tuning_probe(void)
{
}
void mtk_cam_tuning_init(struct mtk_cam_tuning *param)
void mtk_cam_tuning_init(struct mtk_cam_job *job)
{
u8 mirror = IMAGE_NORMAL;
pr_info("%s: platform_id:%u \n", __func__, GET_PLAT_HW(platform_id));
if (!do_set_otp_once) {
@ -1458,7 +1494,17 @@ void mtk_cam_tuning_init(struct mtk_cam_tuning *param)
custom_eeprom_read(&is_otp_valid, (void *)ois_otp);
mtk_set_ois_table(&is_otp_valid, (void *)ois_otp, OTP_SIZE);
if (is_otp_valid) {
oplus_get_sensor_mirror_type(job, &mirror);
}
if (mirror == IMAGE_V_MIRROR) {
oplus_swap_otp_data(ois_otp, swap_ois_otp);
mtk_set_ois_table(&is_otp_valid, (void *)swap_ois_otp, OTP_SIZE);
} else {
mtk_set_ois_table(&is_otp_valid, (void *)ois_otp, OTP_SIZE);
}
pr_info("%s: mirror:%u \n", __func__, mirror);
}
if (GET_PLAT_HW(platform_id) == 6899) {

6
vendor/mediatek/kernel_modules/mtkcam/camsys/isp8/cam/mtk_cam-tuning.h vendored
View File

@ -53,7 +53,7 @@ struct mtk_cam_tuning {
void mtk_cam_tuning_probe(void);
void mtk_cam_tuning_init(struct mtk_cam_tuning *param);
void mtk_cam_tuning_init(struct mtk_cam_job *job);
void mtk_cam_tuning_update(struct mtk_cam_tuning *param);
@ -90,6 +90,10 @@ void oplus_cam_calc_ois_data(struct mtk_cam_tuning *param, struct out_ois_param
void oplus_cam_copy_res(int *pInBuf, struct mtk_cam_tuning *param);
int oplus_cam_poll_ois_thread(void *arg);
void oplus_get_sensor_mirror_type(struct mtk_cam_job *job, u8* mirror);
void oplus_swap_otp_data(unsigned char* ori_otp_data, unsigned char* swap_otp_data);
/*
* oplus's part: end
*/

20
vendor/mediatek/kernel_modules/mtkcam/imgsensor/src-isp8/adaptor-command.c vendored
View File

@ -338,6 +338,23 @@ static int g_cmd_g_sensor_stream_status(struct adaptor_ctx *ctx, void *arg)
return ret;
}
// #define OPLUS_FEATURE_CAMERA_COMMON
static int g_cmd_sensor_mirror_type(struct adaptor_ctx *ctx, void *arg)
{
int ret = 0;
u8 *mirror = NULL;
/* unexpected case, arg is nullptr */
if (unlikely((chk_input_arg(ctx, arg, &ret, __func__)) != 0))
return ret;
mirror = arg;
*mirror = ctx->subctx.s_ctx.mirror;
return ret;
}
// #endif
/* SET */
static int s_cmd_fsync_sync_frame_start_end(struct adaptor_ctx *ctx, void *arg)
@ -622,6 +639,9 @@ static const struct command_entry command_list[] = {
{V4L2_CMD_G_SENSOR_VC_INFO_BY_SCENARIO, g_cmd_sensor_vc_info_by_scenario},
{V4L2_CMD_G_SENSOR_STREAM_STATUS, g_cmd_g_sensor_stream_status},
{V4L2_CMD_G_SENSOR_FAKE_SENSOR_INFO, g_cmd_fake_sensor_info},
// #define OPLUS_FEATURE_CAMERA_COMMON
{V4L2_CMD_GET_SENSOR_MIRROR_TYPE, g_cmd_sensor_mirror_type},
// #endif
/* SET */
{V4L2_CMD_FSYNC_SYNC_FRAME_START_END, s_cmd_fsync_sync_frame_start_end},

18
vendor/mediatek/kernel_modules/mtkcam/imgsensor/src-isp8/adaptor-drv.c vendored
View File

@ -58,10 +58,6 @@ MODULE_PARM_DESC(sensor_debug, "imgsensor_debug");
unsigned int gSensor_num;
unsigned int is_multicam;
unsigned int is_imgsensor_fusion_test_workaround;
#ifdef OPLUS_FEATURE_CAMERA_COMMON
extern struct mutex dw9786_mutex;
bool dw9786_mutex_init_flag = false;
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
static void get_outfmt_code(struct adaptor_ctx *ctx)
{
@ -1539,13 +1535,6 @@ static int imgsensor_probe(struct i3c_i2c_device *client)
mutex_init(&ctx->mutex);
mutex_init(&ctx->ebd_lock);
mutex_init(&ctx->subctx.i2c_buffer_lock);
#ifdef OPLUS_FEATURE_CAMERA_COMMON
if (!dw9786_mutex_init_flag) {
mutex_init(&dw9786_mutex);
adaptor_loge(ctx, "dw9786_mutex init\n");
dw9786_mutex_init_flag = true;
}
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
if (sentest_probe_init(ctx))
adaptor_loge(ctx, "sentest_probe_init return failed\n");
@ -1785,13 +1774,6 @@ static void imgsensor_remove(struct i3c_i2c_device *client)
device_remove_file(ctx->dev, &dev_attr_debug_sensor_mode_ops);
mutex_destroy(&ctx->mutex);
#ifdef OPLUS_FEATURE_CAMERA_COMMON
if (dw9786_mutex_init_flag) {
mutex_destroy(&dw9786_mutex);
adaptor_loge(ctx, "dw9786_mutex destroy\n");
dw9786_mutex_init_flag = false;
}
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
}

65
vendor/mediatek/kernel_modules/mtkcam/imgsensor/src-isp8/adaptor-subdrv-ctrl.c vendored
View File

@ -28,12 +28,6 @@
#include "adaptor-subdrv.h"
#endif
#ifdef OPLUS_FEATURE_CAMERA_COMMON
#define KONKAUTELE_AF_SLAVE_ID 0x32
#define DW9786_CHIP_EN 0xE000
extern struct mutex dw9786_mutex;
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
static const char * const clk_names[] = {
ADAPTOR_CLK_NAMES
};
@ -179,6 +173,28 @@ u64 ixc_table_rewrite(struct subdrv_ctx *ctx, u16 *list, u32 len)
ixc_end = ktime_get_boottime_ns();
return (ixc_end-ixc_start)/1000;
}
static void get_sensor_hw_mode(struct subdrv_ctx *ctx,
enum SENSOR_SCENARIO_ID_ENUM scenario_id, u64 *val) {
u8 *hw_mode = (u8 *)(uintptr_t)(*val);
if (scenario_id >= ctx->s_ctx.sensor_mode_num) {
DRV_LOGE(ctx, "invalid sid:%u, mode_num:%u\n",
scenario_id, ctx->s_ctx.sensor_mode_num);
scenario_id = SENSOR_SCENARIO_ID_NORMAL_PREVIEW;
}
*hw_mode = ctx->s_ctx.mode[scenario_id].hw_mode;
}
static void get_sensor_buffer_increase(struct subdrv_ctx *ctx,
enum SENSOR_SCENARIO_ID_ENUM scenario_id, u64 *val) {
u8 *buffer_increase = (u8 *)(uintptr_t)(*val);
if (scenario_id >= ctx->s_ctx.sensor_mode_num) {
DRV_LOGE(ctx, "invalid sid:%u, mode_num:%u\n",
scenario_id, ctx->s_ctx.sensor_mode_num);
scenario_id = SENSOR_SCENARIO_ID_NORMAL_PREVIEW;
}
*buffer_increase = ctx->s_ctx.mode[scenario_id].buffer_increase;
}
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
static void dump_i2c_buf(struct subdrv_ctx *ctx)
@ -366,38 +382,12 @@ bool probe_eeprom(struct subdrv_ctx *ctx)
u32 header_id = 0;
u32 addr_header_id = 0;
struct eeprom_info_struct *info = ctx->s_ctx.eeprom_info;
#ifdef OPLUS_FEATURE_CAMERA_COMMON
unsigned short stdby[17] = {0x0100, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000};
u16 dw9786_status;
int ret = 0;
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
if (info == NULL) {
DRV_LOG_MUST(ctx, "sensor no support eeprom\n");
return FALSE;
}
#ifdef OPLUS_FEATURE_CAMERA_COMMON
if(ctx->s_ctx.sensor_id == KONKAUTELE_SENSOR_ID) {
mutex_lock(&dw9786_mutex);
DRV_LOG_MUST(ctx, "dw9786_mutex: %p\n", &dw9786_mutex);
ret = adaptor_i2c_rd_u16(ctx->i2c_client, KONKAUTELE_AF_SLAVE_ID>> 1, DW9786_CHIP_EN, &dw9786_status);
DRV_LOG_MUST(ctx, "DW9786_CHIP_EN: 0x%x, ret: %d\n", dw9786_status, ret);
if (dw9786_status != 1) {
DRV_LOG_MUST(ctx, "dw9786 probe_eeprom open read protect\n");
adaptor_i2c_wr_u16(ctx->i2c_client, KONKAUTELE_AF_SLAVE_ID>> 1, DW9786_CHIP_EN, 0x0000);
mdelay(2);
adaptor_i2c_wr_p8(ctx->i2c_client, KONKAUTELE_AF_SLAVE_ID>> 1, DW9786_CHIP_EN, (unsigned char *)stdby, 34);
mdelay(5);
adaptor_i2c_wr_u16(ctx->i2c_client, KONKAUTELE_AF_SLAVE_ID>> 1, 0xE004, 0x0001);
mdelay(20);
}
mutex_unlock(&dw9786_mutex);
}
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
eeprom_num = ctx->s_ctx.eeprom_num;
if (ctx->eeprom_index < ctx->s_ctx.eeprom_num) {
DRV_LOG_MUST(ctx, "index:%u\n", ctx->eeprom_index);
@ -4511,6 +4501,14 @@ int common_feature_control(struct subdrv_ctx *ctx, MSDK_SENSOR_FEATURE_ENUM feat
(u64 *)(feature_data + 1));
break;
case SENSOR_FEATURE_GET_HW_MODE:
get_sensor_hw_mode(ctx,
(enum SENSOR_SCENARIO_ID_ENUM)*(feature_data),
feature_data + 1);
break;
case SENSOR_FEATURE_GET_BUFFER_INCREASE:
get_sensor_buffer_increase(ctx,
(enum SENSOR_SCENARIO_ID_ENUM)*(feature_data),
feature_data + 1);
break;
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
default:
@ -4915,4 +4913,5 @@ void get_sensor_setting_info(struct subdrv_ctx *ctx,
(void *)&ctx->s_ctx.mode[scenario_id].sensor_setting_info,
sizeof(struct SENSOR_SETTING_INFO_STRUCT));
}
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/

1
vendor/mediatek/kernel_modules/mtkcam/imgsensor/src-isp8/adaptor-subdrv.h vendored
View File

@ -294,6 +294,7 @@ struct subdrv_mode_struct {
#ifdef OPLUS_FEATURE_CAMERA_COMMON
struct SENSOR_SETTING_INFO_STRUCT sensor_setting_info;
u8 hw_mode;//2:DC MODE, 1:OTF MODE, 0:defalut
u8 buffer_increase;// 1:need increase, 0:no increase
#endif /*OPLUS_FEATURE_CAMERA_COMMON*/
};

20
vendor/mediatek/kernel_modules/mtkcam/imgsensor/src-v4l2/adaptor-command.c vendored Normal file → Executable file
View File

@ -299,6 +299,23 @@ static int g_cmd_sensor_vc_info_by_scenario(struct adaptor_ctx *ctx, void *arg)
return ret;
}
// #define OPLUS_FEATURE_CAMERA_COMMON
static int g_cmd_sensor_mirror_type(struct adaptor_ctx *ctx, void *arg)
{
int ret = 0;
u8 *mirror = NULL;
/* unexpected case, arg is nullptr */
if (unlikely((chk_input_arg(ctx, arg, &ret, __func__)) != 0))
return ret;
mirror = arg;
*mirror = ctx->subctx.s_ctx.mirror;
return ret;
}
// #endif
/* SET */
static int s_cmd_fsync_sync_frame_start_end(struct adaptor_ctx *ctx, void *arg)
{
@ -481,6 +498,9 @@ static const struct command_entry command_list[] = {
{V4L2_CMD_G_SENSOR_FRAME_CNT, g_cmd_sensor_frame_cnt},
{V4L2_CMD_G_SENSOR_GLP_DT, g_cmd_sensor_glp_dt},
{V4L2_CMD_G_SENSOR_VC_INFO_BY_SCENARIO, g_cmd_sensor_vc_info_by_scenario},
// #define OPLUS_FEATURE_CAMERA_COMMON
{V4L2_CMD_GET_SENSOR_MIRROR_TYPE, g_cmd_sensor_mirror_type},
// #endif
/* SET */
{V4L2_CMD_FSYNC_SYNC_FRAME_START_END, s_cmd_fsync_sync_frame_start_end},

20
vendor/mediatek/kernel_modules/mtkcam/imgsensor/src_spm-isp8/adaptor-command.c vendored Normal file → Executable file
View File

@ -300,6 +300,23 @@ static int g_cmd_sensor_vc_info_by_scenario(struct adaptor_ctx *ctx, void *arg)
return ret;
}
// #define OPLUS_FEATURE_CAMERA_COMMON
static int g_cmd_sensor_mirror_type(struct adaptor_ctx *ctx, void *arg)
{
int ret = 0;
u8 *mirror = NULL;
/* unexpected case, arg is nullptr */
if (unlikely((chk_input_arg(ctx, arg, &ret, __func__)) != 0))
return ret;
mirror = arg;
*mirror = ctx->subctx.s_ctx.mirror;
return ret;
}
// #endif
/* SET */
static int s_cmd_fsync_sync_frame_start_end(struct adaptor_ctx *ctx, void *arg)
{
@ -485,6 +502,9 @@ static const struct command_entry command_list[] = {
{V4L2_CMD_G_SENSOR_FRAME_CNT, g_cmd_sensor_frame_cnt},
{V4L2_CMD_G_SENSOR_GLP_DT, g_cmd_sensor_glp_dt},
{V4L2_CMD_G_SENSOR_VC_INFO_BY_SCENARIO, g_cmd_sensor_vc_info_by_scenario},
// #define OPLUS_FEATURE_CAMERA_COMMON
{V4L2_CMD_GET_SENSOR_MIRROR_TYPE, g_cmd_sensor_mirror_type},
// #endif
/* SET */
{V4L2_CMD_FSYNC_SYNC_FRAME_START_END, s_cmd_fsync_sync_frame_start_end},

21
vendor/mediatek/kernel_modules/mtkcam/imgsys/imgsys/cmdq/isp8/mtk_imgsys-cmdq-qos.c vendored
View File

@ -210,6 +210,7 @@ void mtk_imgsys_mmqos_set_by_scen_plat8(struct mtk_imgsys_dev *imgsys_dev,
u64 bw_final[4] = {0};
u32 sidx = 0;
const u32 step = imgsys_qos_update_freq;
uint8_t boost = frm_info->user_info[0].boost;
frm_num = frm_info->total_frmnum;
hw_comb = frm_info->user_info[frm_num-1].hw_comb;
@ -220,12 +221,12 @@ void mtk_imgsys_mmqos_set_by_scen_plat8(struct mtk_imgsys_dev *imgsys_dev,
if (imgsys_cmdq_is_stream_off() == 0 && isSet == 1) {
if (imgsys_qos_dbg_enable_plat8())
dev_info(qos_info->dev,
"imgsys_qos: frame_no:%d req_cnt:%lu fps:%d vss:%d\n",
"imgsys_qos: frame_no:%d req_cnt:%lu fps:%d vss:%d boost:0x%X\n",
frm_info->frame_no, qos_info->req_cnt,
fps, dvfs_info->vss_task_cnt);
fps, dvfs_info->vss_task_cnt, boost);
if (dvfs_info->vss_task_cnt > 0 &&
qos_info->qos_path[IMGSYS_COMMON_0_R].bw < IMGSYS_QOS_MAX_PERF) {
if ((dvfs_info->vss_task_cnt > 0 || boost == 0xFF) &&
qos_info->qos_path[IMGSYS_COMMON_0_R].bw < IMGSYS_QOS_MAX_PERF) {
qos_info->qos_path[IMGSYS_COMMON_0_R].bw = IMGSYS_QOS_MAX_PERF;
qos_info->qos_path[IMGSYS_COMMON_0_W].bw = IMGSYS_QOS_MAX_PERF;
qos_info->qos_path[IMGSYS_COMMON_1_R].bw = IMGSYS_QOS_MAX_PERF;
@ -298,7 +299,8 @@ void mtk_imgsys_mmqos_set_by_scen_plat8(struct mtk_imgsys_dev *imgsys_dev,
qos_info->bw_avg[1][1] += bw_final[3];
qos_info->avg_cnt++;
if (dvfs_info->vss_task_cnt == 0 &&
if ((dvfs_info->vss_task_cnt == 0) &&
(boost != 0xFF) &&
((qos_info->avg_cnt >= step) ||
(qos_info->req_cnt <= 1))) {
/* unit is MB/s */
@ -351,6 +353,15 @@ void mtk_imgsys_mmqos_set_by_scen_plat8(struct mtk_imgsys_dev *imgsys_dev,
}
}
if (boost == 0xFF) {
/* reset QoS info */
qos_info->req_cnt = 0;
qos_info->avg_cnt = 0;
qos_info->bw_avg[0][0] = 0;
qos_info->bw_avg[0][1] = 0;
qos_info->bw_avg[1][0] = 0;
qos_info->bw_avg[1][1] = 0;
}
}
}

2
vendor/mediatek/kernel_modules/mtkcam/imgsys/imgsys/isp8/mtk-img-ipi.h vendored
View File

@ -149,7 +149,7 @@ struct img_swfrm_info {
uint64_t sw_bwoft;
int subfrm_idx;
void *g_swbuf;
void *bw_swbuf;
uint64_t boost;
uint64_t pixel_bw;
int tunmeta_size;
struct private_data priv[IMGSYS_MAX];

7
vendor/mediatek/kernel_modules/mtkcam/imgsys/imgsys/isp8/mtk_imgsys-sys.c vendored
View File

@ -756,9 +756,9 @@ static void cmdq_cb_done_worker(struct work_struct *work)
&swbuf_data, sizeof(struct img_sw_buffer),
gwork->reqfd, 0);
else
imgsys_send(pipe->imgsys_dev->scp_pdev, HCP_IMGSYS_DEQUE_DONE_ID,
&swbuf_data, sizeof(struct img_sw_buffer),
gwork->reqfd, 0);
imgsys_send(pipe->imgsys_dev->scp_pdev, HCP_IMGSYS_DEQUE_DONE_ID,
&swbuf_data, sizeof(struct img_sw_buffer),
gwork->reqfd, 0);
wake_up_interruptible(&frm_info_waitq);
@ -2236,7 +2236,6 @@ unsigned int mode = imgsys_streaming;
}
for (i = 0 ; i < swfrm_info->total_frmnum ; i++) {
swfrm_info->user_info[i].g_swbuf = gce_virt + (swfrm_info->user_info[i].sw_goft);
swfrm_info->user_info[i].bw_swbuf = gce_virt + (swfrm_info->user_info[i].sw_bwoft);
}
/*first group in request*/

7
vendor/mediatek/kernel_modules/mtkcam/include/mtk_camera-v4l2-controls-8.h vendored Normal file → Executable file
View File

@ -56,6 +56,10 @@
#define V4L2_MTK_CAM_TG_FLASH_MODE_CONTINUOUS 1
#define V4L2_MTK_CAM_TG_FLASH_MODE_MULTIPLE 2
#ifndef OPLUS_FEATURE_CAMERA_COMMON
#define OPLUS_FEATURE_CAMERA_COMMON
#endif
struct mtk_cam_shutter_gain {
__u32 shutter;
__u32 gain;
@ -235,6 +239,9 @@ struct mtk_cam_resource_raw_v2 {
__u8 sen_apply_ctrl;
__u64 sen_deadline_ns;
__u8 ois_compensation;
#ifdef OPLUS_FEATURE_CAMERA_COMMON
__u8 buffer_increase;
#endif
};
struct mtk_cam_resource_v2 {

5
vendor/mediatek/kernel_modules/mtkcam/include/mtk_camera-v4l2-controls-common.h vendored
View File

@ -336,6 +336,11 @@ struct mtk_seninf_lbmf_info {
#define V4L2_CMD_G_SENSOR_FAKE_SENSOR_INFO \
(V4L2_CMD_USER_MTK_SENSOR_BASE + 18)
// #define OPLUS_FEATURE_CAMERA_COMMON
#define V4L2_CMD_GET_SENSOR_MIRROR_TYPE \
(V4L2_CMD_USER_MTK_SENSOR_BASE + 19)
// #endif
/**
* TSREC - notify vsync structure
* V4L2_CMD_TSREC_NOTIFY_VSYNC

9
vendor/oplus/kernel/audio/codecs/aw87xxx/aw87xxx.c vendored
View File

@ -503,6 +503,7 @@ uint8_t aw_speaker_get_mode(struct oplus_speaker_device *speaker_device)
case WORK_MODE_RIGHT:
return AW_CTOS_PROFILE_MUSIC;
case WORK_MODE_LEFT_VOICE:
case WORK_MODE_RIGHT_VOICE:
return AW_CTOS_PROFILE_VOICE;
default:
return -EINVAL;
@ -2074,8 +2075,10 @@ exit_device_init_failed:
aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false);
exit_dtsi_parse_failed:
AW_DEV_LOGE(aw87xxx->dev, "pa init failed");
#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
if (gpio_is_valid(aw87xxx->aw_dev.rst_gpio))
gpio_free(aw87xxx->aw_dev.rst_gpio);
devm_gpio_free(aw87xxx->dev, aw87xxx->aw_dev.rst_gpio);
#endif
#ifdef OPLUS_ARCH_EXTENDS
// add for AW87xxx_2_X_0
i2c_set_clientdata(client, NULL);
@ -2103,8 +2106,10 @@ static int aw87xxx_i2c_remove(struct i2c_client *client)
oplus_speaker_pa_unregister(aw87xxx->oplus_dev_node);
#endif /*CONFIG_SND_SOC_OPLUS_PA_MANAGER*/
#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
if (gpio_is_valid(aw87xxx->aw_dev.rst_gpio))
gpio_free(aw87xxx->aw_dev.rst_gpio);
devm_gpio_free(aw87xxx->dev, aw87xxx->aw_dev.rst_gpio);
#endif
if (aw87xxx->dev_index == 0)
aw87xxx_algo_auth_misc_deinit(&aw87xxx->aw_dev);

36
vendor/oplus/kernel/audio/codecs/aw882xx_v1.13.0/aw882xx.c vendored
View File

@ -3821,6 +3821,34 @@ range_err:
return ret;
}
static ssize_t aw882xx_dbgfs_auto_cali_re(struct file *file,
char __user *user_buf, size_t count,
loff_t *ppos)
{
struct i2c_client *i2c = PDE_DATA(file_inode(file));
struct aw882xx *aw882xx = i2c_get_clientdata(i2c);
char *str = NULL;
int ret = 0;
if (!aw882xx) {
pr_err("%s aw882xx is null\n", __func__);
return -EINVAL;
}
str = kzalloc(PAGE_SIZE, GFP_KERNEL);
if (!str) {
ret = -ENOMEM;
pr_err("[0x%x] memory allocation failed\n", aw882xx->i2c->addr);
goto cali_re_err;
}
ret = oplus_aw_cali_re(&i2c->dev, str);
pr_info("%s addr 0x%x, str=%s\n", __func__, aw882xx->i2c->addr, str);
ret = simple_read_from_buffer(user_buf, count, ppos, str, ret);
kfree(str);
cali_re_err:
return ret;
}
static const struct proc_ops aw882xx_dbgfs_range_fops = {
.proc_open = simple_open,
.proc_read = aw882xx_dbgfs_range_read,
@ -3857,6 +3885,12 @@ static const struct proc_ops aw882xx_dbgfs_f0_show_fops = {
.proc_lseek = default_llseek,
};
static const struct proc_ops aw882xx_dbgfs_auto_cali_re_fops = {
.proc_open = simple_open,
.proc_read = aw882xx_dbgfs_auto_cali_re,
.proc_lseek = default_llseek,
};
static void aw882xx_debug_init(struct aw882xx *aw882xx, struct i2c_client *i2c)
{
char name[50];
@ -3870,6 +3904,8 @@ static void aw882xx_debug_init(struct aw882xx *aw882xx, struct i2c_client *i2c)
&aw882xx_dbgfs_cali_re_fops, i2c);
proc_create_data("r_impedance", S_IRUGO, aw882xx->dbg_dir,
&aw882xx_dbgfs_cali_r_impedance_fops, i2c);
proc_create_data("auto_cali_re", S_IRUGO, aw882xx->dbg_dir,
&aw882xx_dbgfs_auto_cali_re_fops, i2c);
#ifdef AW_NEED_CALIB_F0
if (aw882xx->need_f0_cali) {
proc_create_data("f0_range", S_IRUGO, aw882xx->dbg_dir,

7
vendor/oplus/kernel/audio/codecs/aw882xx_v1.13.0/aw882xx_calib.c vendored
View File

@ -1608,6 +1608,13 @@ static ssize_t aw_range_re_show(struct device *dev,
return len;
}
ssize_t oplus_aw_cali_re(struct device *dev, char *buf)
{
pr_info("[awinic] %s: cali re only.\n",
__func__);
return oplus_cali_re_f0_show(dev, buf, AW_CALI_CMD_RE);
}
#endif /*OPLUS_ARCH_EXTENDS*/
/*set cali time*/

1
vendor/oplus/kernel/audio/codecs/aw882xx_v1.13.0/aw882xx_calib.h vendored
View File

@ -209,6 +209,7 @@ bool aw882xx_cali_check_result(struct aw_cali_desc *cali_desc);
void oplus_aw882xx_cali_set_pa_number(unsigned char total_pa_number);
ssize_t oplus_aw_calib_re_show(struct device *dev, char *buf);
ssize_t oplus_aw_cali_re_f0(struct device *dev, char *buf);
ssize_t oplus_aw_cali_re(struct device *dev, char *buf);
int aw_cali_svc_get_devs_cali_re(struct aw_device *aw_dev, int32_t *re_buf, int num);
int aw_cali_svc_get_devs_cali_f0(struct aw_device *aw_dev, int32_t *f0_buf, int num);
int aw_cali_svc_set_devs_re_str(struct aw_device *aw_dev, const char *re_str);

57
vendor/oplus/kernel/audio/codecs/sipa/sipa.c vendored
View File

@ -106,7 +106,7 @@
/* OWI_POLARITY 0 : pulse level == high, 1 : pulse level == low */
#define OWI_POLARITY (SIA81XX_DISABLE_LEVEL)
// #define DISTINGUISH_CHIP_TYPE
#define DISTINGUISH_CHIP_TYPE
// #define OWI_SUPPORT_WRITE_DATA
#ifdef OWI_SUPPORT_WRITE_DATA
#define OWI_DATA_BIG_END
@ -3550,6 +3550,10 @@ static int sipa_probe(struct platform_device *pdev)
sipa_dev_t *si_pa = NULL;
char work_name[20];
char *sipa_fw_name = "sipa.bin";
#if IS_ENABLED(CONFIG_SND_SOC_OPLUS_PA_MANAGER)
struct oplus_spk_dev_node *spk_dev_node = NULL;
struct oplus_speaker_device *speaker_device = NULL;
#endif /* CONFIG_SND_SOC_OPLUS_PA_MANAGER */
#ifdef CONFIG_SND_SOC_OPLUS_PA_MANAGER
oplus_speaker_probe_lock();
@ -3619,6 +3623,51 @@ static int sipa_probe(struct platform_device *pdev)
/* load firmware */
sipa_param_load_fw(&pdev->dev, sipa_fw_name);
}
#if IS_ENABLED(CONFIG_SND_SOC_OPLUS_PA_MANAGER)
if (IS_SUPPORT_OWI_TYPE(si_pa->chip_type)) {
if (speaker_device == NULL) {
pr_info("[ info][%s] %s():speaker_device == null ,oplus_register start\r\n", LOG_FLAG, __func__);
speaker_device = kzalloc(sizeof(struct oplus_speaker_device), GFP_KERNEL);
if ( speaker_device != NULL) {
speaker_device->speaker_manufacture = MFR_SI;
speaker_device->chipset = si_pa->chip_type;
speaker_device->type = L_SPK + si_pa->channel_num;
speaker_device->speaker_enable_set = sipa_speaker_enable;
speaker_device->speaker_enable_get = sipa_get_speaker_status;
#ifndef OPLUS_AUDIO_PA_BOOST_VOLTAGE
speaker_device->boost_voltage_set = NULL;
#else
speaker_device->boost_voltage_set = sipa_volme_boost_set;
#endif
speaker_device->boost_voltage_get = NULL;
#ifndef OPLUS_FEATURE_SPEAKER_MUTE
speaker_device->speaker_mute_set = NULL;
#else /* OPLUS_FEATURE_SPEAKER_MUTE */
speaker_device->speaker_mute_set = sipa_speaker_mute_set;
#endif /* OPLUS_FEATURE_SPEAKER_MUTE */
speaker_device->speaker_mute_get = NULL;
#if IS_ENABLED(CONFIG_OPLUS_FEATURE_MM_FEEDBACK)
speaker_device->speaker_check_feeback_set = sipa_speaker_check_feeback_set;
speaker_device->speaker_check_feeback_get = sipa_speaker_check_feeback_get;
#else
speaker_device->speaker_check_feeback_set = NULL;
speaker_device->speaker_check_feeback_get = NULL;
#endif
spk_dev_node = oplus_speaker_pa_register(speaker_device);
if (spk_dev_node == NULL) {
pr_err("[err][%s] %s:,oplus_register fail \r\n",LOG_FLAG, __func__);
kfree(speaker_device);
} else {
si_pa->oplus_dev_node = spk_dev_node;
pr_info("[info][%s] %s():,oplus_register end\r\n", LOG_FLAG, __func__);
}
}else {
pr_err("[err][%s] %s:,spk device kzalloc failed \r\n",LOG_FLAG, __func__);
}
}
}
#endif /* CONFIG_SND_SOC_OPLUS_PA_MANAGER */
pr_info("[ info][%s] %s: finish, channel:%d\r\n", LOG_FLAG, __func__, si_pa->channel_num);
#ifdef CONFIG_SND_SOC_OPLUS_PA_MANAGER
oplus_speaker_probe_unlock();
@ -3666,7 +3715,11 @@ static int sipa_remove(struct platform_device *pdev)
si_pa = (sipa_dev_t *)dev_get_drvdata(&pdev->dev);
if (NULL == si_pa)
return 0;
#ifdef CONFIG_SND_SOC_OPLUS_PA_MANAGER
if (IS_SUPPORT_OWI_TYPE(si_pa->chip_type)) {
oplus_speaker_pa_unregister(si_pa->oplus_dev_node);
}
#endif /* CONFIG_SND_SOC_OPLUS_PA_MANAGER */
#ifdef LOAD_FW_BY_DELAY_WORK
cancel_delayed_work_sync(&si_pa->fw_load_work);
#endif

1
vendor/oplus/kernel/audio/oplus_audio_kernel_modules.mk vendored
View File

@ -47,6 +47,7 @@ AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/oplus_audio_tfa98xx_v6.ko
AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/oplus_audio_sipa.ko
AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/oplus_audio_sipa_tuning.ko
AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/oplus_audio_pa_manager.ko
AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/oplus_audio_aw87xxx.ko
# add for audio daemon kernel on QCOM platform sun
AUDIO_KERNEL_MODULES += $(KERNEL_MODULES_OUT)/oplus_audio_daemon.ko
# add for audio netlink kernel communication

1
vendor/oplus/kernel/audio/oplus_audio_kernel_product_board.mk vendored
View File

@ -47,6 +47,7 @@ PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/oplus_audio_tfa98xx_v6.ko
PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/oplus_audio_sipa.ko
PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/oplus_audio_sipa_tuning.ko
PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/oplus_audio_pa_manager.ko
PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/oplus_audio_aw87xxx.ko
# add for audio daemon kernel on QCOM platform sun
PRODUCT_PACKAGES += $(KERNEL_MODULES_OUT)/oplus_audio_daemon.ko
# add for audio netlink kernel communication

85
vendor/oplus/kernel/audio/qcom/oplus_speaker_manager/oplus_speaker_manager.c vendored
View File

@ -33,7 +33,7 @@ const char *const ext_amp_vdd_need[] = { "None", "Need" };
const char *const ext_amp_boost_vol_text[] = {"Level_1", "Level_2", "Level_3", "Level_4"};
const char *const ext_amp_speaker_switch_function[] = { "Off", "On" };
const char *const ext_rcv_amp_function[] = { "Off", "On" };
const char *const ext_amp_speaker_mode_function[] = { "Off", "Music", "Voice", "Fm", "Rcv", "Left", "Right", "Left_Voice"};
const char *const ext_amp_speaker_mode_function[] = { "Off", "Music", "Voice", "Fm", "Rcv", "Left", "Right", "Left_Voice", "Right_Voice"};
const char *const ext_amp_voice_function[] = { "Off", "On" };
const char *const ext_amp_mute_function[] = { "Off", "On" };
const char *const ext_amp_check_feedback[] = { "Off", "On" };
@ -59,6 +59,7 @@ static const struct snd_kcontrol_new oplus_pa_manager_snd_controls[] = {
SOC_ENUM_EXT("SpeakerL_Amp_Switch", (oplus_amp_control_enum)[0], speaker_l_amp_get, speaker_l_amp_set),
SOC_ENUM_EXT("SpeakerR_Amp_Switch", (oplus_amp_control_enum)[0], speaker_r_amp_get, speaker_r_amp_set),
SOC_ENUM_EXT("Rcv_Amp_Switch", (oplus_amp_control_enum)[1], rcv_amp_get, rcv_amp_set),
SOC_ENUM_EXT("RcvL_Amp_Switch", (oplus_amp_control_enum)[1], rcv_l_amp_get, rcv_l_amp_set),
SOC_ENUM_EXT("Ext_Amp_Mode", (oplus_amp_control_enum)[2], ext_amp_mode_get, ext_amp_mode_set),
SOC_ENUM_EXT("Ext_Amp_Vdd_Need", (oplus_amp_control_enum)[3], ext_amp_vdd_get, ext_amp_vdd_set),
SOC_ENUM_EXT("Ext_Amp_Boost_Volume", (oplus_amp_control_enum)[4], ext_amp_boost_volume_get, ext_amp_boost_volume_set),
@ -340,6 +341,85 @@ int rcv_amp_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontr
return 0;
}
int rcv_l_amp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
struct oplus_speaker_device *speaker_device = get_speaker_dev(L_SPK);
ucontrol->value.integer.value[0] = 0;
if (speaker_device == NULL) {
pr_err("%s, %d, speaker_device == NULL\n", __func__, __LINE__);
return -ENODEV;
} else if (contrl_status == NULL) {
pr_err("%s, %d, contrl_status == NULL\n", __func__, __LINE__);
return -ENOMEM;
} else {
ucontrol->value.integer.value[0] = contrl_status->rcv_enable;
}
pr_debug("%s, %d, status = %ld\n", __func__, __LINE__, ucontrol->value.integer.value[0]);
return 0;
}
int rcv_l_amp_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
int value = ucontrol->value.integer.value[0];
enum oplus_pa_work_mode work_mode = WORK_MODE_OFF;
int protection_needed = 0;
struct oplus_speaker_device *speaker_device = get_speaker_dev(L_SPK);
int ret = 0;
if (value == 0) {
work_mode = WORK_MODE_OFF;
} else {
work_mode = WORK_MODE_RECEIVER;
protection_needed = 1;
}
if (speaker_device == NULL) {
pr_err("%s, %d, speaker_device == NULL\n", __func__, __LINE__);
return -ENODEV;
} else if (contrl_status == NULL) {
pr_err("%s, %d, contrl_status == NULL\n", __func__, __LINE__);
} else {
if (speaker_device->speaker_enable_set != NULL) {
pr_debug("%s, %d, speaker_device->speaker_status = %d, contrl_status->rcv_enable = %d\n",
__func__, __LINE__, speaker_device->speaker_status, contrl_status->rcv_enable);
if (speaker_device->speaker_mode != work_mode) {
pr_debug("%s, %d, channel = %d, value = %d, contrl_status->amp_mode_setting = %d\n",
__func__, __LINE__, R_SPK - L_SPK, value, contrl_status->amp_mode_setting);
speaker_device->speaker_mode = work_mode;
ret = speaker_device->speaker_enable_set(speaker_device, value);
if (ret != 0) {
pr_err("%s, %d, ret = %d\n", __func__, __LINE__, ret);
speaker_device->speaker_mode = WORK_MODE_OFF;
} else {
contrl_status->amp_mode_setting = work_mode;
contrl_status->rcv_enable = (speaker_device->speaker_mode == WORK_MODE_RECEIVER) ? 1:0;
}
if (speaker_device->speaker_protection_set != NULL) {
pr_debug("%s, %d, channel = %d, value = %d\n", __func__, __LINE__, R_SPK - L_SPK, protection_needed);
speaker_device->speaker_protection_set(speaker_device, protection_needed);
}
}
} else {
pr_debug("%s, %d, channel = %d, speaker_mode_set == NULL\n", __func__, __LINE__, R_SPK - L_SPK);
}
}
return 0;
}
int ext_amp_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
ucontrol->value.integer.value[0] = 0;
@ -548,7 +628,8 @@ int oplus_spkr_pa_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcon
} else if ((contrl_status->amp_mode_setting == WORK_MODE_LEFT)
|| (contrl_status->amp_mode_setting == WORK_MODE_LEFT_VOICE)) {
oplus_speaker_amp_set(L_SPK, WORK_STATUS_ON);
} else if (contrl_status->amp_mode_setting == WORK_MODE_RIGHT) {
} else if ((contrl_status->amp_mode_setting == WORK_MODE_RIGHT)
|| (contrl_status->amp_mode_setting == WORK_MODE_RIGHT_VOICE)) {
oplus_speaker_amp_set(R_SPK, WORK_STATUS_ON);
} else {
oplus_speaker_amp_set(L_SPK, WORK_STATUS_ON);

2
vendor/oplus/kernel/audio/qcom/oplus_speaker_manager/oplus_speaker_manager.h vendored
View File

@ -31,6 +31,8 @@ int speaker_r_amp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *
int speaker_r_amp_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
int rcv_amp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
int rcv_amp_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
int rcv_l_amp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
int rcv_l_amp_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
int ext_amp_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
int ext_amp_mode_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
int ext_amp_vdd_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);

1
vendor/oplus/kernel/audio/qcom/oplus_speaker_manager/oplus_speaker_manager_codec.h vendored
View File

@ -47,6 +47,7 @@ enum oplus_pa_work_mode {
WORK_MODE_LEFT,
WORK_MODE_RIGHT,
WORK_MODE_LEFT_VOICE,
WORK_MODE_RIGHT_VOICE,
WORK_MODE_COUNT,
};

852
vendor/oplus/kernel/camera/cam_cal/layout/brzafront_op_eeprom.c vendored
View File

@ -1,852 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#define PFX "CAM_CAL_BRZAFRONT"
#define pr_fmt(fmt) PFX "[%s] " fmt, __func__
#include <linux/kernel.h>
#include "cam_cal_list.h"
#include "eeprom_i2c_common_driver.h"
#include "eeprom_i2c_custom_driver.h"
#include "cam_cal_config.h"
#include "oplus_kd_imgsensor.h"
#define READ_4000K 0
static unsigned int do_single_lsc_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
static unsigned int do_2a_gain_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
static unsigned int do_lens_id_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
static unsigned int do_pdaf_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
//static unsigned int layout_check_brzafront(struct EEPROM_DRV_FD_DATA *pdata, unsigned int sensorID, unsigned int *_cfg);
static struct STRUCT_CALIBRATION_LAYOUT_STRUCT cal_layout_table = {
0x00000006, 0x01c40055, CAM_CAL_SINGLE_EEPROM_DATA,
{
{0x00000001, 0x00000000, 0x00000000, do_module_version},
{0x00000001, 0x00000000, 0x00000002, do_part_number},
{0x00000001, 0x00000530, 0x0000074C, do_single_lsc_brzafront},
{0x00000001, 0x00000007, 0x0000000E, do_2a_gain_brzafront}, //Start address, block size is useless
{0x00000001, 0x00000000, 0x00000000, do_pdaf_brzafront},
{0x00000000, 0x00000000, 0x00000000, do_stereo_data},
{0x00000001, 0x00000000, 0x00002000, do_dump_all},
{0x00000001, 0x00000008, 0x00000002, do_lens_id_brzafront}
}
};
struct STRUCT_CAM_CAL_CONFIG_STRUCT brzafront_op_eeprom = {
.name = "brzafront_op_eeprom",
// .check_layout_function = layout_check_brzafront,
.check_layout_function = layout_check,
.read_function = Common_read_region,
.layout = &cal_layout_table,
.sensor_id = BRZAFRONT_SENSOR_ID,
.i2c_write_id = 0xA8,
.max_size = 0x1FFF,
.enable_preload = 1,
.preload_size = 0x1FFF,
};
//static struct STRUCT_CAM_CAL_CONFIG_STRUCT *cam_cal_config = &brzafront_op_eeprom;
/*
unsigned int do_pdaf_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
int err = CamCalReturnErr[pCamCalData->Command];
pCamCalData->PDAF.Size_of_PDAF = block_size;
debug_log("PDAF start_addr =%x table_size=%d\n", start_addr, block_size);
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
start_addr, block_size, (unsigned char *)&pCamCalData->PDAF.Data[0]);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
debug_log("======================PDAF Data==================\n");
debug_log("First five %x, %x, %x, %x, %x\n",
pCamCalData->PDAF.Data[0],
pCamCalData->PDAF.Data[1],
pCamCalData->PDAF.Data[2],
pCamCalData->PDAF.Data[3],
pCamCalData->PDAF.Data[4]);
debug_log("RETURN = 0x%x\n", err);
debug_log("======================PDAF Data==================\n");
return err;
}
*/
static unsigned int do_pdaf_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData){
return 0;
}
#if 0
#define BRZAFRONT_HVBIN_PDAF_PROC1_SIZE (0x1BA0-0x17D0) //976 0x3D0
#define BRZAFRONT_HVBIN_PDAF_PROC2_SIZE (0x2208-0x1BB0) //1624 2600 0xA28
#define BRZAFRONT_HVBIN_PDAF_PROC1_ADDR (0x17D0)
#define BRZAFRONT_HVBIN_PDAF_PROC2_ADDR (0x1BB0)
//partial PD
#define BRZAFRONT_PARTIAL_PD_PROC1_SIZE (0x3590-0x33A0) //496 0X1F0
#define BRZAFRONT_PARTIAL_PD_PROC2_SIZE (0x398C-0x35A0) //1004 1500 0x5DC
#define BRZAFRONT_PARTIAL_PD_PROC1_ADDR (0x33A0)
#define BRZAFRONT_PARTIAL_PD_PROC2_ADDR (0x35A0)
unsigned int do_pdaf_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
return err;
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
int err = CamCalReturnErr[pCamCalData->Command];
unsigned char isValid = 0;
int bios = 0;
bool partial_pd_proc1_flag = false;
bool partial_pd_proc2_flag = false;
bool qpd_proc1_flag = false;
bool qpd_proc2_flag = false;
pCamCalData->PDAF.Size_of_PDAF = 0;
debug_log("======================PDAF Data==================\n");
debug_log("[%s] QPD proc1 start_addr =%x table_size=%d\n", __FUNCTION__, BRZAFRONT_HVBIN_PDAF_PROC1_ADDR, BRZAFRONT_HVBIN_PDAF_PROC1_SIZE);
debug_log("[%s] QPD proc2 start_addr =%x table_size=%d\n", __FUNCTION__, BRZAFRONT_HVBIN_PDAF_PROC2_ADDR, BRZAFRONT_HVBIN_PDAF_PROC2_SIZE);
debug_log("[%s] partial PD proc1 start_addr =%x table_size=%d\n", __FUNCTION__, BRZAFRONT_PARTIAL_PD_PROC1_ADDR, BRZAFRONT_PARTIAL_PD_PROC1_SIZE);
debug_log("[%s] partial PD proc2 start_addr =%x table_size=%d\n", __FUNCTION__, BRZAFRONT_PARTIAL_PD_PROC2_ADDR, BRZAFRONT_PARTIAL_PD_PROC2_SIZE);
// partial PD
isValid = 0;
bios = 0;
// partial PD proc1
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAFRONT_PARTIAL_PD_PROC1_ADDR + BRZAFRONT_PARTIAL_PD_PROC1_SIZE,
1, (unsigned char *)&isValid);
if(isValid != 1) {
debug_log("[%s] partial PD proc1 unvalid\n", __FUNCTION__);
} else {
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAFRONT_PARTIAL_PD_PROC1_ADDR, BRZAFRONT_PARTIAL_PD_PROC1_SIZE,
(unsigned char *)&pCamCalData->PDAF.Data[bios]);
if (read_data_size > 0) {
debug_log("[%s] partial PD proc1 First five %x, %x, %x, %x, %x\n",
__FUNCTION__,
pCamCalData->PDAF.Data[bios],
pCamCalData->PDAF.Data[bios + 1],
pCamCalData->PDAF.Data[bios + 2],
pCamCalData->PDAF.Data[bios + 3],
pCamCalData->PDAF.Data[bios + 4]);
bios += BRZAFRONT_PARTIAL_PD_PROC1_SIZE;
partial_pd_proc1_flag = true;
debug_log("[%s] bios = %d 0x%x\n",__FUNCTION__, bios, bios);
}
}
if(partial_pd_proc1_flag) {
// partial PD proc2
isValid = 0;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAFRONT_PARTIAL_PD_PROC2_ADDR + BRZAFRONT_PARTIAL_PD_PROC2_SIZE,
1, (unsigned char *)&isValid);
if(isValid != 1) {
debug_log("[%s] proc2 unvalid\n", __FUNCTION__);
} else {
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAFRONT_PARTIAL_PD_PROC2_ADDR, BRZAFRONT_PARTIAL_PD_PROC2_SIZE,
(unsigned char *)&pCamCalData->PDAF.Data[bios]);
if (read_data_size > 0) {
debug_log("[%s] partial PD proc2 First five %x, %x, %x, %x, %x\n",
__FUNCTION__,
pCamCalData->PDAF.Data[bios],
pCamCalData->PDAF.Data[bios + 1],
pCamCalData->PDAF.Data[bios + 2],
pCamCalData->PDAF.Data[bios + 3],
pCamCalData->PDAF.Data[bios + 4]);
bios += BRZAFRONT_PARTIAL_PD_PROC2_SIZE;
partial_pd_proc2_flag = true;
debug_log("[%s] bios = %d 0x%x\n",__FUNCTION__, bios, bios);
}
}
}
if(partial_pd_proc1_flag && partial_pd_proc2_flag) {
pCamCalData->PDAF.Size_of_PDAF = bios;
} else {
bios = pCamCalData->PDAF.Size_of_PDAF;
debug_log("[%s] partial PD eeprom error",__FUNCTION__);
}
err = CAM_CAL_ERR_NO_ERR;
// QPD
// QPD proc1
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAFRONT_HVBIN_PDAF_PROC1_ADDR + BRZAFRONT_HVBIN_PDAF_PROC1_SIZE,
1, (unsigned char *)&isValid);
if(isValid != 1) {
debug_log("[%s] QPD proc1 unvalid\n", __FUNCTION__);
} else {
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAFRONT_HVBIN_PDAF_PROC1_ADDR, BRZAFRONT_HVBIN_PDAF_PROC1_SIZE,
(unsigned char *)&pCamCalData->PDAF.Data[bios]);
if (read_data_size > 0) {
debug_log("[%s] QDP proc1 First five %x, %x, %x, %x, %x\n",
__FUNCTION__,
pCamCalData->PDAF.Data[bios],
pCamCalData->PDAF.Data[bios + 1],
pCamCalData->PDAF.Data[bios + 2],
pCamCalData->PDAF.Data[bios + 3],
pCamCalData->PDAF.Data[bios + 4]);
bios += BRZAFRONT_HVBIN_PDAF_PROC1_SIZE;
qpd_proc1_flag = true;
debug_log("[%s] bios = %d 0x%x\n",__FUNCTION__, bios, bios);
}
}
// QPD proc2
if(qpd_proc1_flag) {
isValid = 0;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAFRONT_HVBIN_PDAF_PROC2_ADDR + BRZAFRONT_HVBIN_PDAF_PROC2_SIZE,
1, (unsigned char *)&isValid);
if(isValid != 1) {
debug_log("[%s] QPD proc2 unvalid\n", __FUNCTION__);
}
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAFRONT_HVBIN_PDAF_PROC2_ADDR, BRZAFRONT_HVBIN_PDAF_PROC2_SIZE,
(unsigned char *)&pCamCalData->PDAF.Data[bios]);
if (read_data_size > 0) {
debug_log("[%s] QDP proc2 First five %x, %x, %x, %x, %x\n",
__FUNCTION__,
pCamCalData->PDAF.Data[bios],
pCamCalData->PDAF.Data[bios + 1],
pCamCalData->PDAF.Data[bios + 2],
pCamCalData->PDAF.Data[bios + 3],
pCamCalData->PDAF.Data[bios + 4]);
bios += BRZAFRONT_HVBIN_PDAF_PROC2_SIZE;
qpd_proc2_flag = true;
debug_log("[%s] bios = %d 0x%x\n",__FUNCTION__, bios, bios);
}
}
if(qpd_proc1_flag && qpd_proc2_flag) {
pCamCalData->PDAF.Size_of_PDAF = bios;
} else {
bios = pCamCalData->PDAF.Size_of_PDAF;
debug_log("[%s] QPD eeprom error",__FUNCTION__);
}
if(pCamCalData->PDAF.Size_of_PDAF == 0) {
err = CamCalReturnErr[pCamCalData->Command];
}
debug_log("[%s] pCamCalData->PDAF.Size_of_PDAF= %d 0x%x\n", __FUNCTION__,
pCamCalData->PDAF.Size_of_PDAF, pCamCalData->PDAF.Size_of_PDAF);
debug_log("RETURN = 0x%x\n", err);
debug_log("======================PDAF Data==================\n");
return err;
}
#endif
static unsigned int do_single_lsc_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
unsigned int err = CamCalReturnErr[pCamCalData->Command];
unsigned short table_size;
if (pCamCalData->DataVer >= CAM_CAL_TYPE_NUM) {
err = CAM_CAL_ERR_NO_DEVICE;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
return err;
}
if (block_size != CAM_CAL_SINGLE_LSC_SIZE)
error_log("block_size(%d) is not match (%d)\n",
block_size, CAM_CAL_SINGLE_LSC_SIZE);
pCamCalData->SingleLsc.LscTable.MtkLcsData.MtkLscType = 2;//mtk type
pCamCalData->SingleLsc.LscTable.MtkLcsData.PixId = 8;
table_size = 1868;
pr_debug("lsc table_size %d\n", table_size);
pCamCalData->SingleLsc.LscTable.MtkLcsData.TableSize = table_size;
if (table_size > 0) {
pCamCalData->SingleLsc.TableRotation = 0;
debug_log("u4Offset=%d u4Length=%d", start_addr, table_size);
read_data_size = read_data(pdata,
pCamCalData->sensorID, pCamCalData->deviceID,
start_addr, table_size, (unsigned char *)
&pCamCalData->SingleLsc.LscTable.MtkLcsData.SlimLscType);
if (table_size == read_data_size)
err = CAM_CAL_ERR_NO_ERR;
else {
error_log("Read Failed\n");
err = CamCalReturnErr[pCamCalData->Command];
show_cmd_error_log(pCamCalData->Command);
}
}
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("======================SingleLsc Data==================\n");
pr_debug("[1st] = %x, %x, %x, %x\n",
pCamCalData->SingleLsc.LscTable.Data[0],
pCamCalData->SingleLsc.LscTable.Data[1],
pCamCalData->SingleLsc.LscTable.Data[2],
pCamCalData->SingleLsc.LscTable.Data[3]);
pr_debug("[1st] = SensorLSC(1)?MTKLSC(2)? %x\n",
pCamCalData->SingleLsc.LscTable.MtkLcsData.MtkLscType);
pr_debug("CapIspReg =0x%x, 0x%x, 0x%x, 0x%x, 0x%x",
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[0],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[1],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[2],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[3],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[4]);
pr_debug("RETURN = 0x%x\n", err);
pr_debug("======================SingleLsc Data==================\n");
#endif
return err;
}
static unsigned int do_2a_gain_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
unsigned int err = CamCalReturnErr[pCamCalData->Command];
long long CalGain, FacGain, CalValue;
unsigned char AWBAFConfig = 0xf;
//unsigned short AFInf, AFMacro, AF_50cm;
int tempMax = 0;
int CalR = 1, CalGr = 1, CalGb = 1, CalG = 1, CalB = 1;
int FacR = 1, FacGr = 1, FacGb = 1, FacG = 1, FacB = 1;
int rgCalValue = 1, bgCalValue = 1;
unsigned int awb_offset;
(void) start_addr;
(void) block_size;
pr_debug("In %s: sensor_id=%x\n", __func__, pCamCalData->sensorID);
memset((void *)&pCamCalData->Single2A, 0, sizeof(struct STRUCT_CAM_CAL_SINGLE_2A_STRUCT));
/* Check rule */
if (pCamCalData->DataVer >= CAM_CAL_TYPE_NUM) {
err = CAM_CAL_ERR_NO_DEVICE;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
return err;
}
/* Check AWB & AF enable bit */
pCamCalData->Single2A.S2aVer = 0x01;
pCamCalData->Single2A.S2aBitEn = (0x03 & AWBAFConfig);
pCamCalData->Single2A.S2aAfBitflagEn = (0x0C & AWBAFConfig);
debug_log("S2aBitEn=0x%02x", pCamCalData->Single2A.S2aBitEn);
/* AWB Calibration Data*/
if (0x1 & AWBAFConfig) {
pCamCalData->Single2A.S2aAwb.rGainSetNum = 0x02;
awb_offset = 0x60;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalValue);
if (read_data_size > 0) {
debug_log( "Read CalValue OK\n");
printk("awb Calibration OK tanhao");
rgCalValue = CalValue & 0xFFFF;
bgCalValue = (CalValue >> 16) & 0xFFFF;
debug_log("Light source calibration 5100K value R/G:%d, B/G:%d",rgCalValue, bgCalValue);
printk("brzaLight source calibration 5100K value R/G:%d, B/G:%d",rgCalValue, bgCalValue);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
printk("awb Calibration 5100k OK tanhao");
show_cmd_error_log(pCamCalData->Command);
}
/* AWB Unit Gain (5000K) */
debug_log("5000K AWB\n");
awb_offset = 0x0010;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalGain);
if (read_data_size > 0) {
debug_log("Read CalGain OK %x\n", read_data_size);
CalR = CalGain & 0xFFFF;
CalGr = (CalGain >> 16) & 0xFFFF;
CalGb = (CalGain >> 32) & 0xFFFF;
CalG = ((CalGr + CalGb) + 1) >> 1;
CalB = (CalGain >> 48) & 0xFFFF;
CalR = CalR * rgCalValue / 1000;
CalB = CalB * bgCalValue / 1000;
if (CalR > CalG)
/* R > G */
if (CalR > CalB)
tempMax = CalR;
else
tempMax = CalB;
else
/* G > R */
if (CalG > CalB)
tempMax = CalG;
else
tempMax = CalB;
debug_log("UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
printk("brza5000k UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
printk("brza5000k fail UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
show_cmd_error_log(pCamCalData->Command);
}
if (CalGain != 0x0000000000000000 &&
CalGain != 0xFFFFFFFFFFFFFFFF &&
CalR != 0x00000000 &&
CalG != 0x00000000 &&
CalB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGainSetNum = 1;
pCamCalData->Single2A.S2aAwb.rUnitGainu4R =
(unsigned int)((tempMax * 512 + (CalR >> 1)) / CalR);
pCamCalData->Single2A.S2aAwb.rUnitGainu4G =
(unsigned int)((tempMax * 512 + (CalG >> 1)) / CalG);
pCamCalData->Single2A.S2aAwb.rUnitGainu4B =
(unsigned int)((tempMax * 512 + (CalB >> 1)) / CalB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!\n");
pr_debug("Unit R=%d G=%d B=%d!!\n", CalR, CalG, CalB);
}
/* AWB Golden Gain (5000K) */
awb_offset = 0x0018;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&FacGain);
if (read_data_size > 0) {
debug_log("Read FacGain OK\n");
FacR = FacGain & 0xFFFF;
FacGr = (FacGain >> 16) & 0xFFFF;
FacGb = (FacGain >> 32) & 0xFFFF;
FacG = ((FacGr + FacGb) + 1) >> 1;
FacB = (FacGain >> 48) & 0xFFFF;
if (FacR > FacG)
if (FacR > FacB)
tempMax = FacR;
else
tempMax = FacB;
else
if (FacG > FacB)
tempMax = FacG;
else
tempMax = FacB;
debug_log("GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
printk("brzaGoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read FacGain Failed\n");
printk("brzafail GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
show_cmd_error_log(pCamCalData->Command);
}
if (FacGain != 0x0000000000000000 &&
FacGain != 0xFFFFFFFFFFFFFFFF &&
FacR != 0x00000000 &&
FacG != 0x00000000 &&
FacB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGoldGainu4R =
(unsigned int)((tempMax * 512 + (FacR >> 1)) / FacR);
pCamCalData->Single2A.S2aAwb.rGoldGainu4G =
(unsigned int)((tempMax * 512 + (FacG >> 1)) / FacG);
pCamCalData->Single2A.S2aAwb.rGoldGainu4B =
(unsigned int)((tempMax * 512 + (FacB >> 1)) / FacB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!");
pr_debug("Golden R=%d G=%d B=%d\n", FacR, FacG, FacB);
}
/* Set AWB to 3A Layer */
pCamCalData->Single2A.S2aAwb.rValueR = CalR;
pCamCalData->Single2A.S2aAwb.rValueGr = CalGr;
pCamCalData->Single2A.S2aAwb.rValueGb = CalGb;
pCamCalData->Single2A.S2aAwb.rValueB = CalB;
pCamCalData->Single2A.S2aAwb.rGoldenR = FacR;
pCamCalData->Single2A.S2aAwb.rGoldenGr = FacGr;
pCamCalData->Single2A.S2aAwb.rGoldenGb = FacGb;
pCamCalData->Single2A.S2aAwb.rGoldenB = FacB;
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("======================AWB CAM_CAL==================\n");
pr_debug("AWB Calibration @5100K\n");
pr_debug("[CalGain] = 0x%x\n", CalGain);
pr_debug("[FacGain] = 0x%x\n", FacGain);
pr_debug("[rCalGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4R);
pr_debug("[rCalGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4G);
pr_debug("[rCalGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4B);
pr_debug("[rFacGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4R);
pr_debug("[rFacGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4G);
pr_debug("[rFacGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4B);
#endif
/* AWB Unit Gain (4000K) */
#if READ_4000K //zemin.lai@CamTuning delet ,module not support 4000k otp 20220421
CalR = 0;
CalGr = 0;
CalGb = 0;
CalG = 0;
CalB = 0;
tempMax = 0;
debug_log("4000K AWB\n");
awb_offset = 0x32;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalGain);
if (read_data_size > 0) {
debug_log("Read CalGain OK %x\n", read_data_size);
CalR = CalGain & 0xFFFF;
CalGr = (CalGain >> 16) & 0xFFFF;
CalGb = (CalGain >> 32) & 0xFFFF;
CalG = ((CalGr + CalGb) + 1) >> 1;
CalB = (CalGain >> 48) & 0xFFFF;
if (CalR > CalG)
/* R > G */
if (CalR > CalB)
tempMax = CalR;
else
tempMax = CalB;
else
/* G > R */
if (CalG > CalB)
tempMax = CalG;
else
tempMax = CalB;
debug_log(
"UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (CalGain != 0x0000000000000000 &&
CalGain != 0xFFFFFFFFFFFFFFFF &&
CalR != 0x00000000 &&
CalG != 0x00000000 &&
CalB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rUnitGainu4R_mid =
(unsigned int)((tempMax * 512 + (CalR >> 1)) / CalR);
pCamCalData->Single2A.S2aAwb.rUnitGainu4G_mid =
(unsigned int)((tempMax * 512 + (CalG >> 1)) / CalG);
pCamCalData->Single2A.S2aAwb.rUnitGainu4B_mid =
(unsigned int)((tempMax * 512 + (CalB >> 1)) / CalB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!\n");
pr_debug("Unit R=%d G=%d B=%d!!\n", CalR, CalG, CalB);
}
/* AWB Golden Gain (4000K) */
FacR = 0;
FacGr = 0;
FacGb = 0;
FacG = 0;
FacB = 0;
tempMax = 0;
awb_offset = 0x3A;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&FacGain);
if (read_data_size > 0) {
debug_log("Read FacGain OK\n");
FacR = FacGain & 0xFFFF;
FacGr = (FacGain >> 16) & 0xFFFF;
FacGb = (FacGain >> 32) & 0xFFFF;
FacG = ((FacGr + FacGb) + 1) >> 1;
FacB = (FacGain >> 48) & 0xFFFF;
if (FacR > FacG)
if (FacR > FacB)
tempMax = FacR;
else
tempMax = FacB;
else
if (FacG > FacB)
tempMax = FacG;
else
tempMax = FacB;
debug_log("GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read FacGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (FacGain != 0x0000000000000000 &&
FacGain != 0xFFFFFFFFFFFFFFFF &&
FacR != 0x00000000 &&
FacG != 0x00000000 &&
FacB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGoldGainu4R_mid =
(unsigned int)((tempMax * 512 + (FacR >> 1)) / FacR);
pCamCalData->Single2A.S2aAwb.rGoldGainu4G_mid =
(unsigned int)((tempMax * 512 + (FacG >> 1)) / FacG);
pCamCalData->Single2A.S2aAwb.rGoldGainu4B_mid =
(unsigned int)((tempMax * 512 + (FacB >> 1)) / FacB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!");
pr_debug("Golden R=%d G=%d B=%d\n", FacR, FacG, FacB);
}
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("AWB Calibration @4000K\n");
pr_debug("[CalGain] = 0x%x\n", CalGain);
pr_debug("[FacGain] = 0x%x\n", FacGain);
pr_debug("[rCalGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4R_mid);
pr_debug("[rCalGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4G_mid);
pr_debug("[rCalGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4B_mid);
pr_debug("[rFacGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4R_mid);
pr_debug("[rFacGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4G_mid);
pr_debug("[rFacGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4B_mid);
#endif
#endif
/* AWB Calibration Data*/
CalR = 0;
CalGr = 0;
CalGb = 0;
CalG = 0;
CalB = 0;
tempMax = 0;
debug_log("2850K AWB\n");
rgCalValue = 0;
bgCalValue = 0;
awb_offset = 0x006C;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalValue);
if (read_data_size > 0) {
debug_log( "Read CalValue OK\n");
rgCalValue = CalValue & 0xFFFF;
bgCalValue = (CalValue >> 16) & 0xFFFF;
debug_log("Light source calibration value 3100 R/G:%d, B/G:%d",rgCalValue, bgCalValue);
printk("brzaLight source calibration value 3100 R/G:%d, B/G:%d",rgCalValue, bgCalValue);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
printk("brzafail Light source calibration value 3100 R/G:%d, B/G:%d",rgCalValue, bgCalValue);
show_cmd_error_log(pCamCalData->Command);
}
/* AWB Unit Gain (3100K) */
awb_offset = 0x0034;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalGain);
if (read_data_size > 0) {
debug_log("Read CalGain OK %x\n", read_data_size);
CalR = CalGain & 0xFFFF;
CalGr = (CalGain >> 16) & 0xFFFF;
CalGb = (CalGain >> 32) & 0xFFFF;
CalG = ((CalGr + CalGb) + 1) >> 1;
CalB = (CalGain >> 48) & 0xFFFF;
debug_log("CalR:%d, CalB:%d",CalR, CalB);
CalR = CalR * rgCalValue / 1000;
CalB = CalB * bgCalValue / 1000;
if (CalR > CalG)
/* R > G */
if (CalR > CalB)
tempMax = CalR;
else
tempMax = CalB;
else
/* G > R */
if (CalG > CalB)
tempMax = CalG;
else
tempMax = CalB;
debug_log("UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (CalGain != 0x0000000000000000 &&
CalGain != 0xFFFFFFFFFFFFFFFF &&
CalR != 0x00000000 &&
CalG != 0x00000000 &&
CalB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGainSetNum = 2;
pCamCalData->Single2A.S2aAwb.rUnitGainu4R_low =
(unsigned int)((tempMax * 512 + (CalR >> 1)) / CalR);
pCamCalData->Single2A.S2aAwb.rUnitGainu4G_low =
(unsigned int)((tempMax * 512 + (CalG >> 1)) / CalG);
pCamCalData->Single2A.S2aAwb.rUnitGainu4B_low =
(unsigned int)((tempMax * 512 + (CalB >> 1)) / CalB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!\n");
pr_debug("Unit R=%d G=%d B=%d!!\n", CalR, CalG, CalB);
}
/* AWB Golden Gain (3100K) */
FacR = 0;
FacGr = 0;
FacGb = 0;
FacG = 0;
FacB = 0;
tempMax = 0;
awb_offset = 0x003C;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&FacGain);
if (read_data_size > 0) {
debug_log("Read FacGain OK\n");
FacR = FacGain & 0xFFFF;
FacGr = (FacGain >> 16) & 0xFFFF;
FacGb = (FacGain >> 32) & 0xFFFF;
FacG = ((FacGr + FacGb) + 1) >> 1;
FacB = (FacGain >> 48) & 0xFFFF;
if (FacR > FacG)
if (FacR > FacB)
tempMax = FacR;
else
tempMax = FacB;
else
if (FacG > FacB)
tempMax = FacG;
else
tempMax = FacB;
debug_log("GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
printk("brzaGoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read FacGain Failed\n");
printk("brzafail GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
show_cmd_error_log(pCamCalData->Command);
}
if (FacGain != 0x0000000000000000 &&
FacGain != 0xFFFFFFFFFFFFFFFF &&
FacR != 0x00000000 &&
FacG != 0x00000000 &&
FacB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGoldGainu4R_low =
(unsigned int)((tempMax * 512 + (FacR >> 1)) / FacR);
pCamCalData->Single2A.S2aAwb.rGoldGainu4G_low =
(unsigned int)((tempMax * 512 + (FacG >> 1)) / FacG);
pCamCalData->Single2A.S2aAwb.rGoldGainu4B_low =
(unsigned int)((tempMax * 512 + (FacB >> 1)) / FacB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!");
pr_debug("Golden R=%d G=%d B=%d\n", FacR, FacG, FacB);
}
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("AWB Calibration @3100K\n");
pr_debug("[CalGain] = 0x%x\n", CalGain);
pr_debug("[FacGain] = 0x%x\n", FacGain);
pr_debug("[rCalGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4R_low);
pr_debug("[rCalGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4G_low);
pr_debug("[rCalGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4B_low);
pr_debug("[rFacGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4R_low);
pr_debug("[rFacGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4G_low);
pr_debug("[rFacGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4B_low);
pr_debug("======================AWB CAM_CAL==================\n");
#endif
}
#if 0
/* AF Calibration Data*/
if (0x2 & AWBAFConfig) {
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
0x96, 2, (unsigned char *)&AF_50cm);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
0x94, 2, (unsigned char *)&AFInf);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
0x92, 2, (unsigned char *)&AFMacro);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
/* AFInf = AFInf >> 2;
AFMacro = AFMacro >> 2;
AF_50cm = AF_50cm >> 2; */
pCamCalData->Single2A.S2aAf[0] = AFInf;
pCamCalData->Single2A.S2aAf[1] = AFMacro;
pCamCalData->Single2A.S2aAf[2] = AF_50cm;
////Only AF Gathering <////
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("======================AF CAM_CAL==================\n");
pr_debug("[AFInf] = %d\n", AFInf);
pr_debug("[AFMacro] = %d\n", AFMacro);
pr_debug("[AF_50cm] = %d\n", AF_50cm);
pr_debug("======================AF CAM_CAL==================\n");
#endif
}
#endif
return err;
}
static unsigned int do_lens_id_brzafront(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
return do_lens_id_base(pdata, start_addr, block_size, pGetSensorCalData);
}
/*
static unsigned int layout_check_brzafront(struct EEPROM_DRV_FD_DATA *pdata, unsigned int sensorID, unsigned int *_cfg)
{
unsigned int header_offset = cam_cal_config->layout->header_addr;
unsigned int check_id = 0x00000000;
unsigned int result = CAM_CAL_ERR_NO_DEVICE;
if (cam_cal_config->sensor_id == sensorID)
debug_log("%s sensor_id matched\n", cam_cal_config->name);
else {
debug_log("%s sensor_id not matched\n", cam_cal_config->name);
return result;
}
if (read_data_region(pdata, (u8 *)&check_id, header_offset, 4) != 4) {
debug_log("header_id read failed\n");
return result;
}
if (check_id == 0x01c40055 || check_id == 0x01C3012B || check_id == 0x00510055) { // hearder id on OTP guide
debug_log("header_id matched 0x%08x\n", check_id);
printk("brzaheader_id matched 0x%08x\n", check_id);
result = CAM_CAL_ERR_NO_ERR;
} else{
debug_log("header_id not matched 0x%08x\n", check_id);
printk("brzaheader_id not matched 0x%08x\n", check_id);
}
return result;
}*/

824
vendor/oplus/kernel/camera/cam_cal/layout/brzamain_op_eeprom.c vendored
View File

@ -1,824 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#define PFX "CAM_CAL_BRZAMAIN"
#define pr_fmt(fmt) PFX "[%s] " fmt, __func__
#include <linux/kernel.h>
#include "cam_cal_list.h"
#include "eeprom_i2c_common_driver.h"
#include "eeprom_i2c_custom_driver.h"
#include "cam_cal_config.h"
#include "oplus_kd_imgsensor.h"
#define READ_4000K 0
#define DEBUG_CALIBRATION_LOAD
static unsigned int do_single_lsc_brzamain(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
static unsigned int do_2a_gain_brzamain(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
static unsigned int do_lens_id_brzamain(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
static unsigned int do_pdaf_brzamain(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
//static unsigned int layout_check_brzamain(struct EEPROM_DRV_FD_DATA *pdata, unsigned int sensorID, unsigned int *_cfg);
static struct STRUCT_CALIBRATION_LAYOUT_STRUCT cal_layout_table = {
0x00000006, 0x016B012B, CAM_CAL_SINGLE_EEPROM_DATA,
{
{0x00000001, 0x00000000, 0x00000000, do_module_version},
{0x00000001, 0x00000000, 0x00000002, do_part_number},
{0x00000001, 0x00001070, 0x0000074C, do_single_lsc_brzamain},
{0x00000001, 0x00000007, 0x0000000E, do_2a_gain_brzamain}, //Start address, block size is useless
{0x00000001, 0x000017D0, 0x00000A3A, do_pdaf_brzamain},
{0x00000000, 0x00000FAE, 0x00000550, do_stereo_data},
{0x00000001, 0x00000000, 0x00008000, do_dump_all},
{0x00000001, 0x00000008, 0x00000002, do_lens_id_brzamain}
}
};
struct STRUCT_CAM_CAL_CONFIG_STRUCT brzamain_op_eeprom = {
.name = "brzamain_op_eeprom",
//.check_layout_function = layout_check_brzamain,
.check_layout_function = layout_check,
.read_function = Common_read_region,
.layout = &cal_layout_table,
.sensor_id = BRZAMAIN_SENSOR_ID,
.i2c_write_id = 0xA0,
.max_size = 0x8000,
.enable_preload = 1,
.preload_size = 0x8000,
};
//static struct STRUCT_CAM_CAL_CONFIG_STRUCT *cam_cal_config = &brzamain_op_eeprom;
/*
unsigned int do_pdaf_brzamain(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
int err = CamCalReturnErr[pCamCalData->Command];
pCamCalData->PDAF.Size_of_PDAF = block_size;
debug_log("PDAF start_addr =%x table_size=%d\n", start_addr, block_size);
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
start_addr, block_size, (unsigned char *)&pCamCalData->PDAF.Data[0]);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
debug_log("======================PDAF Data==================\n");
debug_log("First five %x, %x, %x, %x, %x\n",
pCamCalData->PDAF.Data[0],
pCamCalData->PDAF.Data[1],
pCamCalData->PDAF.Data[2],
pCamCalData->PDAF.Data[3],
pCamCalData->PDAF.Data[4]);
debug_log("RETURN = 0x%x\n", err);
debug_log("======================PDAF Data==================\n");
return err;
}
*/
#define BRZAMAIN_HVBIN_PDAF_PROC1_SIZE (0x1BA0-0x17D0) //976 0x3D0
#define BRZAMAIN_HVBIN_PDAF_PROC2_SIZE (0x2208-0x1BB0) //1624 2600 0xA28
#define BRZAMAIN_HVBIN_PDAF_PROC1_ADDR (0x17D0)
#define BRZAMAIN_HVBIN_PDAF_PROC2_ADDR (0x1BB0)
//partial PD
#define BRZAMAIN_PARTIAL_PD_PROC1_SIZE (0x3590-0x33A0) //496 0X1F0
#define BRZAMAIN_PARTIAL_PD_PROC2_SIZE (0x398C-0x35A0) //1004 1500 0x5DC
#define BRZAMAIN_PARTIAL_PD_PROC1_ADDR (0x33A0)
#define BRZAMAIN_PARTIAL_PD_PROC2_ADDR (0x35A0)
unsigned int do_pdaf_brzamain(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
int err = CamCalReturnErr[pCamCalData->Command];
unsigned char isValid = 0;
int bios = 0;
bool partial_pd_proc1_flag = false;
bool partial_pd_proc2_flag = false;
bool qpd_proc1_flag = false;
bool qpd_proc2_flag = false;
pCamCalData->PDAF.Size_of_PDAF = 0;
debug_log("======================PDAF Data==================\n");
debug_log("[%s] QPD proc1 start_addr =%x table_size=%d\n", __FUNCTION__, BRZAMAIN_HVBIN_PDAF_PROC1_ADDR, BRZAMAIN_HVBIN_PDAF_PROC1_SIZE);
debug_log("[%s] QPD proc2 start_addr =%x table_size=%d\n", __FUNCTION__, BRZAMAIN_HVBIN_PDAF_PROC2_ADDR, BRZAMAIN_HVBIN_PDAF_PROC2_SIZE);
debug_log("[%s] partial PD proc1 start_addr =%x table_size=%d\n", __FUNCTION__, BRZAMAIN_PARTIAL_PD_PROC1_ADDR, BRZAMAIN_PARTIAL_PD_PROC1_SIZE);
debug_log("[%s] partial PD proc2 start_addr =%x table_size=%d\n", __FUNCTION__, BRZAMAIN_PARTIAL_PD_PROC2_ADDR, BRZAMAIN_PARTIAL_PD_PROC2_SIZE);
// partial PD
isValid = 0;
bios = 0;
// partial PD proc1
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAMAIN_PARTIAL_PD_PROC1_ADDR + BRZAMAIN_PARTIAL_PD_PROC1_SIZE,
1, (unsigned char *)&isValid);
if(isValid != 1) {
debug_log("[%s] partial PD proc1 unvalid\n", __FUNCTION__);
} else {
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAMAIN_PARTIAL_PD_PROC1_ADDR, BRZAMAIN_PARTIAL_PD_PROC1_SIZE,
(unsigned char *)&pCamCalData->PDAF.Data[bios]);
if (read_data_size > 0) {
debug_log("[%s] partial PD proc1 First five %x, %x, %x, %x, %x\n",
__FUNCTION__,
pCamCalData->PDAF.Data[bios],
pCamCalData->PDAF.Data[bios + 1],
pCamCalData->PDAF.Data[bios + 2],
pCamCalData->PDAF.Data[bios + 3],
pCamCalData->PDAF.Data[bios + 4]);
bios += BRZAMAIN_PARTIAL_PD_PROC1_SIZE;
partial_pd_proc1_flag = true;
debug_log("[%s] bios = %d 0x%x\n",__FUNCTION__, bios, bios);
}
}
if(partial_pd_proc1_flag) {
// partial PD proc2
isValid = 0;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAMAIN_PARTIAL_PD_PROC2_ADDR + BRZAMAIN_PARTIAL_PD_PROC2_SIZE,
1, (unsigned char *)&isValid);
if(isValid != 1) {
debug_log("[%s] proc2 unvalid\n", __FUNCTION__);
} else {
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAMAIN_PARTIAL_PD_PROC2_ADDR, BRZAMAIN_PARTIAL_PD_PROC2_SIZE,
(unsigned char *)&pCamCalData->PDAF.Data[bios]);
if (read_data_size > 0) {
debug_log("[%s] partial PD proc2 First five %x, %x, %x, %x, %x\n",
__FUNCTION__,
pCamCalData->PDAF.Data[bios],
pCamCalData->PDAF.Data[bios + 1],
pCamCalData->PDAF.Data[bios + 2],
pCamCalData->PDAF.Data[bios + 3],
pCamCalData->PDAF.Data[bios + 4]);
bios += BRZAMAIN_PARTIAL_PD_PROC2_SIZE;
partial_pd_proc2_flag = true;
debug_log("[%s] bios = %d 0x%x\n",__FUNCTION__, bios, bios);
}
}
}
if(partial_pd_proc1_flag && partial_pd_proc2_flag) {
pCamCalData->PDAF.Size_of_PDAF = bios;
} else {
bios = pCamCalData->PDAF.Size_of_PDAF;
debug_log("[%s] partial PD eeprom error",__FUNCTION__);
}
err = CAM_CAL_ERR_NO_ERR;
// QPD
// QPD proc1
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAMAIN_HVBIN_PDAF_PROC1_ADDR + BRZAMAIN_HVBIN_PDAF_PROC1_SIZE,
1, (unsigned char *)&isValid);
if(isValid != 1) {
debug_log("[%s] QPD proc1 unvalid\n", __FUNCTION__);
} else {
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAMAIN_HVBIN_PDAF_PROC1_ADDR, BRZAMAIN_HVBIN_PDAF_PROC1_SIZE,
(unsigned char *)&pCamCalData->PDAF.Data[bios]);
if (read_data_size > 0) {
debug_log("[%s] QDP proc1 First five %x, %x, %x, %x, %x\n",
__FUNCTION__,
pCamCalData->PDAF.Data[bios],
pCamCalData->PDAF.Data[bios + 1],
pCamCalData->PDAF.Data[bios + 2],
pCamCalData->PDAF.Data[bios + 3],
pCamCalData->PDAF.Data[bios + 4]);
bios += BRZAMAIN_HVBIN_PDAF_PROC1_SIZE;
qpd_proc1_flag = true;
debug_log("[%s] bios = %d 0x%x\n",__FUNCTION__, bios, bios);
}
}
// QPD proc2
if(qpd_proc1_flag) {
isValid = 0;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAMAIN_HVBIN_PDAF_PROC2_ADDR + BRZAMAIN_HVBIN_PDAF_PROC2_SIZE,
1, (unsigned char *)&isValid);
if(isValid != 1) {
debug_log("[%s] QPD proc2 unvalid\n", __FUNCTION__);
}
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
BRZAMAIN_HVBIN_PDAF_PROC2_ADDR, BRZAMAIN_HVBIN_PDAF_PROC2_SIZE,
(unsigned char *)&pCamCalData->PDAF.Data[bios]);
if (read_data_size > 0) {
debug_log("[%s] QDP proc2 First five %x, %x, %x, %x, %x\n",
__FUNCTION__,
pCamCalData->PDAF.Data[bios],
pCamCalData->PDAF.Data[bios + 1],
pCamCalData->PDAF.Data[bios + 2],
pCamCalData->PDAF.Data[bios + 3],
pCamCalData->PDAF.Data[bios + 4]);
bios += BRZAMAIN_HVBIN_PDAF_PROC2_SIZE;
qpd_proc2_flag = true;
debug_log("[%s] bios = %d 0x%x\n",__FUNCTION__, bios, bios);
}
}
if(qpd_proc1_flag && qpd_proc2_flag) {
pCamCalData->PDAF.Size_of_PDAF = bios;
} else {
bios = pCamCalData->PDAF.Size_of_PDAF;
debug_log("[%s] QPD eeprom error",__FUNCTION__);
}
if(pCamCalData->PDAF.Size_of_PDAF == 0) {
err = CamCalReturnErr[pCamCalData->Command];
}
debug_log("[%s] pCamCalData->PDAF.Size_of_PDAF= %d 0x%x\n", __FUNCTION__,
pCamCalData->PDAF.Size_of_PDAF, pCamCalData->PDAF.Size_of_PDAF);
debug_log("RETURN = 0x%x\n", err);
debug_log("======================PDAF Data==================\n");
return err;
}
static unsigned int do_single_lsc_brzamain(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
unsigned int err = CamCalReturnErr[pCamCalData->Command];
unsigned short table_size;
if (pCamCalData->DataVer >= CAM_CAL_TYPE_NUM) {
err = CAM_CAL_ERR_NO_DEVICE;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
return err;
}
if (block_size != CAM_CAL_SINGLE_LSC_SIZE)
error_log("block_size(%d) is not match (%d)\n",
block_size, CAM_CAL_SINGLE_LSC_SIZE);
pCamCalData->SingleLsc.LscTable.MtkLcsData.MtkLscType = 2;//mtk type
pCamCalData->SingleLsc.LscTable.MtkLcsData.PixId = 8;
table_size = 1868;
pr_debug("lsc table_size %d\n", table_size);
pCamCalData->SingleLsc.LscTable.MtkLcsData.TableSize = table_size;
if (table_size > 0) {
pCamCalData->SingleLsc.TableRotation = 0;
debug_log("u4Offset=%d u4Length=%d", start_addr, table_size);
read_data_size = read_data(pdata,
pCamCalData->sensorID, pCamCalData->deviceID,
start_addr, table_size, (unsigned char *)
&pCamCalData->SingleLsc.LscTable.MtkLcsData.SlimLscType);
if (table_size == read_data_size)
err = CAM_CAL_ERR_NO_ERR;
else {
error_log("Read Failed\n");
err = CamCalReturnErr[pCamCalData->Command];
show_cmd_error_log(pCamCalData->Command);
}
}
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("======================SingleLsc Data==================\n");
pr_debug("[1st] = %x, %x, %x, %x\n",
pCamCalData->SingleLsc.LscTable.Data[0],
pCamCalData->SingleLsc.LscTable.Data[1],
pCamCalData->SingleLsc.LscTable.Data[2],
pCamCalData->SingleLsc.LscTable.Data[3]);
pr_debug("[1st] = SensorLSC(1)?MTKLSC(2)? %x\n",
pCamCalData->SingleLsc.LscTable.MtkLcsData.MtkLscType);
pr_debug("CapIspReg =0x%x, 0x%x, 0x%x, 0x%x, 0x%x",
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[0],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[1],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[2],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[3],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[4]);
pr_debug("RETURN = 0x%x\n", err);
pr_debug("======================SingleLsc Data==================\n");
#endif
return err;
}
static unsigned int do_2a_gain_brzamain(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
unsigned int err = CamCalReturnErr[pCamCalData->Command];
long long CalGain, FacGain, CalValue;
unsigned char AWBAFConfig = 0xf;
unsigned short AFInf, AFMacro, AF_50cm;
int tempMax = 0;
int CalR = 1, CalGr = 1, CalGb = 1, CalG = 1, CalB = 1;
int FacR = 1, FacGr = 1, FacGb = 1, FacG = 1, FacB = 1;
int rgCalValue = 1, bgCalValue = 1;
unsigned int awb_offset;
(void) start_addr;
(void) block_size;
pr_debug("In %s: sensor_id=%x\n", __func__, pCamCalData->sensorID);
memset((void *)&pCamCalData->Single2A, 0, sizeof(struct STRUCT_CAM_CAL_SINGLE_2A_STRUCT));
/* Check rule */
if (pCamCalData->DataVer >= CAM_CAL_TYPE_NUM) {
err = CAM_CAL_ERR_NO_DEVICE;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
return err;
}
/* Check AWB & AF enable bit */
pCamCalData->Single2A.S2aVer = 0x01;
pCamCalData->Single2A.S2aBitEn = (0x03 & AWBAFConfig);
pCamCalData->Single2A.S2aAfBitflagEn = (0x0C & AWBAFConfig);
debug_log("S2aBitEn=0x%02x", pCamCalData->Single2A.S2aBitEn);
/* AWB Calibration Data*/
if (0x1 & AWBAFConfig) {
pCamCalData->Single2A.S2aAwb.rGainSetNum = 0x02;
awb_offset = 0x60;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalValue);
if (read_data_size > 0) {
debug_log( "Read CalValue OK\n");
rgCalValue = CalValue & 0xFFFF;
bgCalValue = (CalValue >> 16) & 0xFFFF;
debug_log("Light source calibration 5100K value R/G:%d, B/G:%d",rgCalValue, bgCalValue);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
/* AWB Unit Gain (5000K) */
debug_log("5000K AWB\n");
awb_offset = 0x20;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalGain);
if (read_data_size > 0) {
debug_log("Read CalGain OK %x\n", read_data_size);
CalR = CalGain & 0xFFFF;
CalGr = (CalGain >> 16) & 0xFFFF;
CalGb = (CalGain >> 32) & 0xFFFF;
CalG = ((CalGr + CalGb) + 1) >> 1;
CalB = (CalGain >> 48) & 0xFFFF;
CalR = CalR * rgCalValue / 1000;
CalB = CalB * bgCalValue / 1000;
if (CalR > CalG)
/* R > G */
if (CalR > CalB)
tempMax = CalR;
else
tempMax = CalB;
else
/* G > R */
if (CalG > CalB)
tempMax = CalG;
else
tempMax = CalB;
debug_log("UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (CalGain != 0x0000000000000000 &&
CalGain != 0xFFFFFFFFFFFFFFFF &&
CalR != 0x00000000 &&
CalG != 0x00000000 &&
CalB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGainSetNum = 1;
pCamCalData->Single2A.S2aAwb.rUnitGainu4R =
(unsigned int)((tempMax * 512 + (CalR >> 1)) / CalR);
pCamCalData->Single2A.S2aAwb.rUnitGainu4G =
(unsigned int)((tempMax * 512 + (CalG >> 1)) / CalG);
pCamCalData->Single2A.S2aAwb.rUnitGainu4B =
(unsigned int)((tempMax * 512 + (CalB >> 1)) / CalB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!\n");
pr_debug("Unit R=%d G=%d B=%d!!\n", CalR, CalG, CalB);
}
/* AWB Golden Gain (5000K) */
awb_offset = 0x28;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&FacGain);
if (read_data_size > 0) {
debug_log("Read FacGain OK\n");
FacR = FacGain & 0xFFFF;
FacGr = (FacGain >> 16) & 0xFFFF;
FacGb = (FacGain >> 32) & 0xFFFF;
FacG = ((FacGr + FacGb) + 1) >> 1;
FacB = (FacGain >> 48) & 0xFFFF;
if (FacR > FacG)
if (FacR > FacB)
tempMax = FacR;
else
tempMax = FacB;
else
if (FacG > FacB)
tempMax = FacG;
else
tempMax = FacB;
debug_log("GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read FacGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (FacGain != 0x0000000000000000 &&
FacGain != 0xFFFFFFFFFFFFFFFF &&
FacR != 0x00000000 &&
FacG != 0x00000000 &&
FacB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGoldGainu4R =
(unsigned int)((tempMax * 512 + (FacR >> 1)) / FacR);
pCamCalData->Single2A.S2aAwb.rGoldGainu4G =
(unsigned int)((tempMax * 512 + (FacG >> 1)) / FacG);
pCamCalData->Single2A.S2aAwb.rGoldGainu4B =
(unsigned int)((tempMax * 512 + (FacB >> 1)) / FacB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!");
pr_debug("Golden R=%d G=%d B=%d\n", FacR, FacG, FacB);
}
/* Set AWB to 3A Layer */
pCamCalData->Single2A.S2aAwb.rValueR = CalR;
pCamCalData->Single2A.S2aAwb.rValueGr = CalGr;
pCamCalData->Single2A.S2aAwb.rValueGb = CalGb;
pCamCalData->Single2A.S2aAwb.rValueB = CalB;
pCamCalData->Single2A.S2aAwb.rGoldenR = FacR;
pCamCalData->Single2A.S2aAwb.rGoldenGr = FacGr;
pCamCalData->Single2A.S2aAwb.rGoldenGb = FacGb;
pCamCalData->Single2A.S2aAwb.rGoldenB = FacB;
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("======================AWB CAM_CAL==================\n");
pr_debug("AWB Calibration @5100K\n");
pr_debug("[CalGain] = 0x%llx\n", CalGain);
pr_debug("[FacGain] = 0x%llx\n", FacGain);
pr_debug("[rCalGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4R);
pr_debug("[rCalGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4G);
pr_debug("[rCalGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4B);
pr_debug("[rFacGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4R);
pr_debug("[rFacGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4G);
pr_debug("[rFacGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4B);
#endif
/* AWB Unit Gain (4000K) */
#if READ_4000K //zemin.lai@CamTuning delet ,module not support 4000k otp 20220421
CalR = 0;
CalGr = 0;
CalGb = 0;
CalG = 0;
CalB = 0;
tempMax = 0;
debug_log("4000K AWB\n");
awb_offset = 0x32;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalGain);
if (read_data_size > 0) {
debug_log("Read CalGain OK %x\n", read_data_size);
CalR = CalGain & 0xFFFF;
CalGr = (CalGain >> 16) & 0xFFFF;
CalGb = (CalGain >> 32) & 0xFFFF;
CalG = ((CalGr + CalGb) + 1) >> 1;
CalB = (CalGain >> 48) & 0xFFFF;
if (CalR > CalG)
/* R > G */
if (CalR > CalB)
tempMax = CalR;
else
tempMax = CalB;
else
/* G > R */
if (CalG > CalB)
tempMax = CalG;
else
tempMax = CalB;
debug_log(
"UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (CalGain != 0x0000000000000000 &&
CalGain != 0xFFFFFFFFFFFFFFFF &&
CalR != 0x00000000 &&
CalG != 0x00000000 &&
CalB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rUnitGainu4R_mid =
(unsigned int)((tempMax * 512 + (CalR >> 1)) / CalR);
pCamCalData->Single2A.S2aAwb.rUnitGainu4G_mid =
(unsigned int)((tempMax * 512 + (CalG >> 1)) / CalG);
pCamCalData->Single2A.S2aAwb.rUnitGainu4B_mid =
(unsigned int)((tempMax * 512 + (CalB >> 1)) / CalB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!\n");
pr_debug("Unit R=%d G=%d B=%d!!\n", CalR, CalG, CalB);
}
/* AWB Golden Gain (4000K) */
FacR = 0;
FacGr = 0;
FacGb = 0;
FacG = 0;
FacB = 0;
tempMax = 0;
awb_offset = 0x3A;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&FacGain);
if (read_data_size > 0) {
debug_log("Read FacGain OK\n");
FacR = FacGain & 0xFFFF;
FacGr = (FacGain >> 16) & 0xFFFF;
FacGb = (FacGain >> 32) & 0xFFFF;
FacG = ((FacGr + FacGb) + 1) >> 1;
FacB = (FacGain >> 48) & 0xFFFF;
if (FacR > FacG)
if (FacR > FacB)
tempMax = FacR;
else
tempMax = FacB;
else
if (FacG > FacB)
tempMax = FacG;
else
tempMax = FacB;
debug_log("GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read FacGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (FacGain != 0x0000000000000000 &&
FacGain != 0xFFFFFFFFFFFFFFFF &&
FacR != 0x00000000 &&
FacG != 0x00000000 &&
FacB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGoldGainu4R_mid =
(unsigned int)((tempMax * 512 + (FacR >> 1)) / FacR);
pCamCalData->Single2A.S2aAwb.rGoldGainu4G_mid =
(unsigned int)((tempMax * 512 + (FacG >> 1)) / FacG);
pCamCalData->Single2A.S2aAwb.rGoldGainu4B_mid =
(unsigned int)((tempMax * 512 + (FacB >> 1)) / FacB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!");
pr_debug("Golden R=%d G=%d B=%d\n", FacR, FacG, FacB);
}
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("AWB Calibration @4000K\n");
pr_debug("[CalGain] = 0x%llx\n", CalGain);
pr_debug("[FacGain] = 0x%llx\n", FacGain);
pr_debug("[rCalGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4R_mid);
pr_debug("[rCalGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4G_mid);
pr_debug("[rCalGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4B_mid);
pr_debug("[rFacGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4R_mid);
pr_debug("[rFacGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4G_mid);
pr_debug("[rFacGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4B_mid);
#endif
#endif
/* AWB Unit Gain (3100K) */
CalR = 0;
CalGr = 0;
CalGb = 0;
CalG = 0;
CalB = 0;
tempMax = 0;
debug_log("2850K AWB\n");
rgCalValue = 0;
bgCalValue = 0;
awb_offset = 0x6C;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalValue);
if (read_data_size > 0) {
debug_log( "Read CalValue OK\n");
rgCalValue = CalValue & 0xFFFF;
bgCalValue = (CalValue >> 16) & 0xFFFF;
debug_log("Light source calibration value 3100 R/G:%d, B/G:%d",rgCalValue, bgCalValue);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
awb_offset = 0x44;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalGain);
if (read_data_size > 0) {
debug_log("Read CalGain OK %x\n", read_data_size);
CalR = CalGain & 0xFFFF;
CalGr = (CalGain >> 16) & 0xFFFF;
CalGb = (CalGain >> 32) & 0xFFFF;
CalG = ((CalGr + CalGb) + 1) >> 1;
CalB = (CalGain >> 48) & 0xFFFF;
debug_log("CalR:%d, CalB:%d",CalR, CalB);
CalR = CalR * rgCalValue / 1000;
CalB = CalB * bgCalValue / 1000;
if (CalR > CalG)
/* R > G */
if (CalR > CalB)
tempMax = CalR;
else
tempMax = CalB;
else
/* G > R */
if (CalG > CalB)
tempMax = CalG;
else
tempMax = CalB;
debug_log("UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (CalGain != 0x0000000000000000 &&
CalGain != 0xFFFFFFFFFFFFFFFF &&
CalR != 0x00000000 &&
CalG != 0x00000000 &&
CalB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGainSetNum = 2;
pCamCalData->Single2A.S2aAwb.rUnitGainu4R_low =
(unsigned int)((tempMax * 512 + (CalR >> 1)) / CalR);
pCamCalData->Single2A.S2aAwb.rUnitGainu4G_low =
(unsigned int)((tempMax * 512 + (CalG >> 1)) / CalG);
pCamCalData->Single2A.S2aAwb.rUnitGainu4B_low =
(unsigned int)((tempMax * 512 + (CalB >> 1)) / CalB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!\n");
pr_debug("Unit R=%d G=%d B=%d!!\n", CalR, CalG, CalB);
}
/* AWB Golden Gain (3100K) */
FacR = 0;
FacGr = 0;
FacGb = 0;
FacG = 0;
FacB = 0;
tempMax = 0;
awb_offset = 0x4C;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&FacGain);
if (read_data_size > 0) {
debug_log("Read FacGain OK\n");
FacR = FacGain & 0xFFFF;
FacGr = (FacGain >> 16) & 0xFFFF;
FacGb = (FacGain >> 32) & 0xFFFF;
FacG = ((FacGr + FacGb) + 1) >> 1;
FacB = (FacGain >> 48) & 0xFFFF;
if (FacR > FacG)
if (FacR > FacB)
tempMax = FacR;
else
tempMax = FacB;
else
if (FacG > FacB)
tempMax = FacG;
else
tempMax = FacB;
debug_log("GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read FacGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (FacGain != 0x0000000000000000 &&
FacGain != 0xFFFFFFFFFFFFFFFF &&
FacR != 0x00000000 &&
FacG != 0x00000000 &&
FacB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGoldGainu4R_low =
(unsigned int)((tempMax * 512 + (FacR >> 1)) / FacR);
pCamCalData->Single2A.S2aAwb.rGoldGainu4G_low =
(unsigned int)((tempMax * 512 + (FacG >> 1)) / FacG);
pCamCalData->Single2A.S2aAwb.rGoldGainu4B_low =
(unsigned int)((tempMax * 512 + (FacB >> 1)) / FacB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!");
pr_debug("Golden R=%d G=%d B=%d\n", FacR, FacG, FacB);
}
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("AWB Calibration @3100K\n");
pr_debug("[CalGain] = 0x%llx\n", CalGain);
pr_debug("[FacGain] = 0x%llx\n", FacGain);
pr_debug("[rCalGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4R_low);
pr_debug("[rCalGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4G_low);
pr_debug("[rCalGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4B_low);
pr_debug("[rFacGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4R_low);
pr_debug("[rFacGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4G_low);
pr_debug("[rFacGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4B_low);
pr_debug("======================AWB CAM_CAL==================\n");
#endif
}
/* AF Calibration Data*/
if (0x2 & AWBAFConfig) {
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
0x96, 2, (unsigned char *)&AF_50cm);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
0x94, 2, (unsigned char *)&AFInf);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
0x92, 2, (unsigned char *)&AFMacro);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
/* AFInf = AFInf >> 2;
AFMacro = AFMacro >> 2;
AF_50cm = AF_50cm >> 2; */
pCamCalData->Single2A.S2aAf[0] = AFInf;
pCamCalData->Single2A.S2aAf[1] = AFMacro;
pCamCalData->Single2A.S2aAf[2] = AF_50cm;
////Only AF Gathering <////
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("======================AF CAM_CAL==================\n");
pr_debug("[AFInf] = %d\n", AFInf);
pr_debug("[AFMacro] = %d\n", AFMacro);
pr_debug("[AF_50cm] = %d\n", AF_50cm);
pr_debug("======================AF CAM_CAL==================\n");
#endif
}
return err;
}
static unsigned int do_lens_id_brzamain(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
return do_lens_id_base(pdata, start_addr, block_size, pGetSensorCalData);
}
/*
static unsigned int layout_check_brzamain(struct EEPROM_DRV_FD_DATA *pdata, unsigned int sensorID, unsigned int *_cfg)
{
unsigned int header_offset = cam_cal_config->layout->header_addr;
unsigned int check_id = 0x00000000;
unsigned int result = CAM_CAL_ERR_NO_DEVICE;
if (cam_cal_config->sensor_id == sensorID) {
debug_log("%s sensor_id matched\n", cam_cal_config->name);
}
else {
debug_log("%s sensor_id not matched\n", cam_cal_config->name);
return result;
}
if (read_data_region(pdata, (u8 *)&check_id, header_offset, 4) != 4) {
debug_log("header_id read failed\n");
return result;
}
if (check_id == 0x016B012B || check_id == 0x01C3012B) { // hearder id on OTP guide
debug_log("header_id matched 0x%08x\n", check_id);
result = CAM_CAL_ERR_NO_ERR;
} else {
debug_log("header_id not matched 0x%08x\n", check_id);
}
return result;
}*/

622
vendor/oplus/kernel/camera/cam_cal/layout/brzauwide_op_eeprom.c vendored
View File

@ -1,622 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#define PFX "CAM_CAL_BRZAUWIDE"
#define pr_fmt(fmt) PFX "[%s] " fmt, __func__
#include <linux/kernel.h>
#include "cam_cal_list.h"
#include "eeprom_i2c_common_driver.h"
#include "eeprom_i2c_custom_driver.h"
#include "cam_cal_config.h"
#include "oplus_kd_imgsensor.h"
#define DEBUG_CALIBRATION_LOAD
#define pr_debug_if(cond, ...) do { if ((cond)) pr_debug(__VA_ARGS__); } while (0)
#define pr_debug_err(...) pr_debug("error: " __VA_ARGS__)
#define READ_4000K 0
static int dump_enable = 1;
static unsigned int do_single_lsc_brzauwide(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
static unsigned int do_2a_gain_brzauwide(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
static unsigned int do_lens_id_brzauwide(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData);
//static unsigned int layout_check_brzauwide(struct EEPROM_DRV_FD_DATA *pdata, unsigned int sensorID, unsigned int *_cfg);
static struct STRUCT_CALIBRATION_LAYOUT_STRUCT cal_layout_table = {
0x00000006, 0x0065009a, CAM_CAL_SINGLE_EEPROM_DATA,
{
{0x00000001, 0x00000000, 0x00000000, do_module_version},
{0x00000001, 0x00000000, 0x00000002, do_part_number},
{0x00000001, 0x00000530, 0x0000074C, do_single_lsc_brzauwide},
{0x00000001, 0x00000020, 0x0000000E, do_2a_gain_brzauwide}, //Start address, block size is useless
{0x00000000, 0x00000000, 0x00000000, do_pdaf},
{0x00000000, 0x00000FAE, 0x00000550, do_stereo_data},
{0x00000001, 0x00000000, 0x00004000, do_dump_all},
{0x00000001, 0x00000008, 0x00000002, do_lens_id_brzauwide}
}
};
struct STRUCT_CAM_CAL_CONFIG_STRUCT brzauwide_op_eeprom = {
.name = "brzauwide_op_eeprom",
//.check_layout_function = layout_check_brzauwide,
.check_layout_function = layout_check,
.read_function = Common_read_region,
.layout = &cal_layout_table,
.sensor_id = BRZAUWIDE_SENSOR_ID,
.i2c_write_id = 0xA2,
.max_size = 0x4000,
.enable_preload = 1,
.preload_size = 0x4000,
.has_stored_data = 1,
};
//static struct STRUCT_CAM_CAL_CONFIG_STRUCT *cam_cal_config = &brzauwide_op_eeprom;
static unsigned int do_single_lsc_brzauwide(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
unsigned int err = CamCalReturnErr[pCamCalData->Command];
unsigned short table_size;
#ifdef MTK_LOAD_DEBUG
dump_enable = 1;
#else
dump_enable = 0;
#endif
if (pCamCalData->DataVer >= CAM_CAL_TYPE_NUM) {
err = CAM_CAL_ERR_NO_DEVICE;
pr_debug_err("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
return err;
}
if (block_size != CAM_CAL_SINGLE_LSC_SIZE)
pr_debug_err("block_size(%d) is not match (%d)\n",
block_size, CAM_CAL_SINGLE_LSC_SIZE);
pCamCalData->SingleLsc.LscTable.MtkLcsData.MtkLscType = 2;//mtk type
pCamCalData->SingleLsc.LscTable.MtkLcsData.PixId = 8;
table_size = 1868;
pr_debug("lsc table_size %d\n", table_size);
pCamCalData->SingleLsc.LscTable.MtkLcsData.TableSize = table_size;
if (table_size > 0) {
pCamCalData->SingleLsc.TableRotation = 0;
pr_debug_if(dump_enable, "u4Offset=%d u4Length=%d", start_addr, table_size);
read_data_size = read_data(pdata,
pCamCalData->sensorID, pCamCalData->deviceID,
start_addr, table_size, (unsigned char *)
&pCamCalData->SingleLsc.LscTable.MtkLcsData.SlimLscType);
if (table_size == read_data_size)
err = CAM_CAL_ERR_NO_ERR;
else {
pr_debug_err("Read Failed\n");
err = CamCalReturnErr[pCamCalData->Command];
show_cmd_error_log(pCamCalData->Command);
}
}
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("======================SingleLsc Data==================\n");
pr_debug("[1st] = %x, %x, %x, %x\n",
pCamCalData->SingleLsc.LscTable.Data[0],
pCamCalData->SingleLsc.LscTable.Data[1],
pCamCalData->SingleLsc.LscTable.Data[2],
pCamCalData->SingleLsc.LscTable.Data[3]);
pr_debug("[1st] = SensorLSC(1)?MTKLSC(2)? %x\n",
pCamCalData->SingleLsc.LscTable.MtkLcsData.MtkLscType);
pr_debug("CapIspReg =0x%x, 0x%x, 0x%x, 0x%x, 0x%x",
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[0],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[1],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[2],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[3],
pCamCalData->SingleLsc.LscTable.MtkLcsData.CapIspReg[4]);
pr_debug("RETURN = 0x%x\n", err);
pr_debug("======================SingleLsc Data==================\n");
#endif
return err;
}
static unsigned int do_2a_gain_brzauwide(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
struct STRUCT_CAM_CAL_DATA_STRUCT *pCamCalData =
(struct STRUCT_CAM_CAL_DATA_STRUCT *)pGetSensorCalData;
int read_data_size;
unsigned int err = CamCalReturnErr[pCamCalData->Command];
long long CalGain, FacGain, CalValue;
unsigned char AWBAFConfig = 0xf;
unsigned short AFInf, AFMacro;
int tempMax = 0;
int CalR = 1, CalGr = 1, CalGb = 1, CalG = 1, CalB = 1;
int FacR = 1, FacGr = 1, FacGb = 1, FacG = 1, FacB = 1;
int rgCalValue = 1, bgCalValue = 1;
unsigned int awb_offset;
(void) start_addr;
(void) block_size;
#ifdef MTK_LOAD_DEBUG
dump_enable = 1;
#else
dump_enable = 0;
#endif
pr_debug("In %s: sensor_id=%x\n", __func__, pCamCalData->sensorID);
memset((void *)&pCamCalData->Single2A, 0, sizeof(struct STRUCT_CAM_CAL_SINGLE_2A_STRUCT));
/* Check rule */
if (pCamCalData->DataVer >= CAM_CAL_TYPE_NUM) {
err = CAM_CAL_ERR_NO_DEVICE;
pr_debug_err("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
return err;
}
/* Check AWB & AF enable bit */
pCamCalData->Single2A.S2aVer = 0x01;
pCamCalData->Single2A.S2aBitEn = (0x03 & AWBAFConfig);
pCamCalData->Single2A.S2aAfBitflagEn = (0x0C & AWBAFConfig);
pr_debug_if(dump_enable, "S2aBitEn=0x%02x", pCamCalData->Single2A.S2aBitEn);
/* AWB Calibration Data*/
if (0x1 & AWBAFConfig) {
pCamCalData->Single2A.S2aAwb.rGainSetNum = 0x02;
awb_offset = 0x60;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalValue);
if (read_data_size > 0) {
debug_log( "Read CalValue OK\n");
rgCalValue = CalValue & 0xFFFF;
bgCalValue = (CalValue >> 16) & 0xFFFF;
debug_log("Light source calibration 5100K value R/G:%d, B/G:%d",rgCalValue, bgCalValue);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
/* AWB Unit Gain (5100K) */
pr_debug_if(dump_enable, "5100K AWB\n");
awb_offset = 0x20;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalGain);
if (read_data_size > 0) {
pr_debug_if(dump_enable, "Read CalGain OK %x\n", read_data_size);
CalR = CalGain & 0xFFFF;
CalGr = (CalGain >> 16) & 0xFFFF;
CalGb = (CalGain >> 32) & 0xFFFF;
CalG = ((CalGr + CalGb) + 1) >> 1;
CalB = (CalGain >> 48) & 0xFFFF;
CalR = CalR * rgCalValue / 1000;
CalB = CalB * bgCalValue / 1000;
if (CalR > CalG)
/* R > G */
if (CalR > CalB)
tempMax = CalR;
else
tempMax = CalB;
else
/* G > R */
if (CalG > CalB)
tempMax = CalG;
else
tempMax = CalB;
pr_debug_if(dump_enable,
"UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
pr_debug_err("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (CalGain != 0x0000000000000000 &&
CalGain != 0xFFFFFFFFFFFFFFFF &&
CalR != 0x00000000 &&
CalG != 0x00000000 &&
CalB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGainSetNum = 1;
pCamCalData->Single2A.S2aAwb.rUnitGainu4R =
(unsigned int)((tempMax * 512 + (CalR >> 1)) / CalR);
pCamCalData->Single2A.S2aAwb.rUnitGainu4G =
(unsigned int)((tempMax * 512 + (CalG >> 1)) / CalG);
pCamCalData->Single2A.S2aAwb.rUnitGainu4B =
(unsigned int)((tempMax * 512 + (CalB >> 1)) / CalB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!\n");
pr_debug("Unit R=%d G=%d B=%d!!\n", CalR, CalG, CalB);
}
/* AWB Golden Gain (5100K) */
awb_offset = 0x28;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&FacGain);
if (read_data_size > 0) {
pr_debug_if(dump_enable, "Read FacGain OK\n");
FacR = FacGain & 0xFFFF;
FacGr = (FacGain >> 16) & 0xFFFF;
FacGb = (FacGain >> 32) & 0xFFFF;
FacG = ((FacGr + FacGb) + 1) >> 1;
FacB = (FacGain >> 48) & 0xFFFF;
if (FacR > FacG)
if (FacR > FacB)
tempMax = FacR;
else
tempMax = FacB;
else
if (FacG > FacB)
tempMax = FacG;
else
tempMax = FacB;
pr_debug_if(dump_enable,
"GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
pr_debug_err("Read FacGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (FacGain != 0x0000000000000000 &&
FacGain != 0xFFFFFFFFFFFFFFFF &&
FacR != 0x00000000 &&
FacG != 0x00000000 &&
FacB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGoldGainu4R =
(unsigned int)((tempMax * 512 + (FacR >> 1)) / FacR);
pCamCalData->Single2A.S2aAwb.rGoldGainu4G =
(unsigned int)((tempMax * 512 + (FacG >> 1)) / FacG);
pCamCalData->Single2A.S2aAwb.rGoldGainu4B =
(unsigned int)((tempMax * 512 + (FacB >> 1)) / FacB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!");
pr_debug("Golden R=%d G=%d B=%d\n", FacR, FacG, FacB);
}
/* Set AWB to 3A Layer */
pCamCalData->Single2A.S2aAwb.rValueR = CalR;
pCamCalData->Single2A.S2aAwb.rValueGr = CalGr;
pCamCalData->Single2A.S2aAwb.rValueGb = CalGb;
pCamCalData->Single2A.S2aAwb.rValueB = CalB;
pCamCalData->Single2A.S2aAwb.rGoldenR = FacR;
pCamCalData->Single2A.S2aAwb.rGoldenGr = FacGr;
pCamCalData->Single2A.S2aAwb.rGoldenGb = FacGb;
pCamCalData->Single2A.S2aAwb.rGoldenB = FacB;
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("======================AWB CAM_CAL==================\n");
pr_debug("AWB Calibration @5100K\n");
pr_debug("[CalGain] = 0x%llx\n", CalGain);
pr_debug("[FacGain] = 0x%llx\n", FacGain);
pr_debug("[rCalGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4R);
pr_debug("[rCalGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4G);
pr_debug("[rCalGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4B);
pr_debug("[rFacGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4R);
pr_debug("[rFacGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4G);
pr_debug("[rFacGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4B);
#endif
/* AWB Unit Gain (4000K) */
#if READ_4000K //zemin.lai@CamTuning delet ,module not support 4000k otp 20220421
CalR = CalGr = CalGb = CalG = CalB = 0;
tempMax = 0;
pr_debug_if(dump_enable, "4000K AWB\n");
awb_offset = 0x32;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalGain);
if (read_data_size > 0) {
pr_debug_if(dump_enable, "Read CalGain OK %x\n", read_data_size);
CalR = CalGain & 0xFFFF;
CalGr = (CalGain >> 16) & 0xFFFF;
CalGb = (CalGain >> 32) & 0xFFFF;
CalG = ((CalGr + CalGb) + 1) >> 1;
CalB = (CalGain >> 48) & 0xFFFF;
if (CalR > CalG)
/* R > G */
if (CalR > CalB)
tempMax = CalR;
else
tempMax = CalB;
else
/* G > R */
if (CalG > CalB)
tempMax = CalG;
else
tempMax = CalB;
pr_debug_if(dump_enable,
"UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
pr_debug_err("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (CalGain != 0x0000000000000000 &&
CalGain != 0xFFFFFFFFFFFFFFFF &&
CalR != 0x00000000 &&
CalG != 0x00000000 &&
CalB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rUnitGainu4R_mid =
(unsigned int)((tempMax * 512 + (CalR >> 1)) / CalR);
pCamCalData->Single2A.S2aAwb.rUnitGainu4G_mid =
(unsigned int)((tempMax * 512 + (CalG >> 1)) / CalG);
pCamCalData->Single2A.S2aAwb.rUnitGainu4B_mid =
(unsigned int)((tempMax * 512 + (CalB >> 1)) / CalB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!\n");
pr_debug("Unit R=%d G=%d B=%d!!\n", CalR, CalG, CalB);
}
/* AWB Golden Gain (4000K) */
FacR = 0;
FacGr = 0;
FacGb = 0;
FacG = 0;
FacB = 0;
tempMax = 0;
awb_offset = 0x3A;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&FacGain);
if (read_data_size > 0) {
pr_debug_if(dump_enable, "Read FacGain OK\n");
FacR = FacGain & 0xFFFF;
FacGr = (FacGain >> 16) & 0xFFFF;
FacGb = (FacGain >> 32) & 0xFFFF;
FacG = ((FacGr + FacGb) + 1) >> 1;
FacB = (FacGain >> 48) & 0xFFFF;
if (FacR > FacG)
if (FacR > FacB)
tempMax = FacR;
else
tempMax = FacB;
else
if (FacG > FacB)
tempMax = FacG;
else
tempMax = FacB;
pr_debug_if(dump_enable,
"GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
pr_debug_err("Read FacGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (FacGain != 0x0000000000000000 &&
FacGain != 0xFFFFFFFFFFFFFFFF &&
FacR != 0x00000000 &&
FacG != 0x00000000 &&
FacB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGoldGainu4R_mid =
(unsigned int)((tempMax * 512 + (FacR >> 1)) / FacR);
pCamCalData->Single2A.S2aAwb.rGoldGainu4G_mid =
(unsigned int)((tempMax * 512 + (FacG >> 1)) / FacG);
pCamCalData->Single2A.S2aAwb.rGoldGainu4B_mid =
(unsigned int)((tempMax * 512 + (FacB >> 1)) / FacB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!");
pr_debug("Golden R=%d G=%d B=%d\n", FacR, FacG, FacB);
}
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("AWB Calibration @4000K\n");
pr_debug("[CalGain] = 0x%llx\n", CalGain);
pr_debug("[FacGain] = 0x%llx\n", FacGain);
pr_debug("[rCalGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4R_mid);
pr_debug("[rCalGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4G_mid);
pr_debug("[rCalGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4B_mid);
pr_debug("[rFacGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4R_mid);
pr_debug("[rFacGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4G_mid);
pr_debug("[rFacGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4B_mid);
#endif
#endif
/* AWB Unit Gain (3100K) */
CalR = CalGr = CalGb = CalG = CalB = 0;
tempMax = 0;
rgCalValue = 0;
bgCalValue = 0;
awb_offset = 0x6C;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalValue);
if (read_data_size > 0) {
debug_log( "Read CalValue OK\n");
rgCalValue = CalValue & 0xFFFF;
bgCalValue = (CalValue >> 16) & 0xFFFF;
debug_log("Light source calibration value 3100 R/G:%d, B/G:%d",rgCalValue, bgCalValue);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
error_log("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
pr_debug_if(dump_enable, "3100K AWB\n");
awb_offset = 0x44;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&CalGain);
if (read_data_size > 0) {
pr_debug_if(dump_enable, "Read CalGain OK %x\n", read_data_size);
CalR = CalGain & 0xFFFF;
CalGr = (CalGain >> 16) & 0xFFFF;
CalGb = (CalGain >> 32) & 0xFFFF;
CalG = ((CalGr + CalGb) + 1) >> 1;
CalB = (CalGain >> 48) & 0xFFFF;
CalR = CalR * rgCalValue / 1000;
CalB = CalB * bgCalValue / 1000;
if (CalR > CalG)
/* R > G */
if (CalR > CalB)
tempMax = CalR;
else
tempMax = CalB;
else
/* G > R */
if (CalG > CalB)
tempMax = CalG;
else
tempMax = CalB;
pr_debug_if(dump_enable,
"UnitR:%d, UnitG:%d, UnitB:%d, New Unit Max=%d",
CalR, CalG, CalB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
pr_debug_err("Read CalGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (CalGain != 0x0000000000000000 &&
CalGain != 0xFFFFFFFFFFFFFFFF &&
CalR != 0x00000000 &&
CalG != 0x00000000 &&
CalB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGainSetNum = 2;
pCamCalData->Single2A.S2aAwb.rUnitGainu4R_low =
(unsigned int)((tempMax * 512 + (CalR >> 1)) / CalR);
pCamCalData->Single2A.S2aAwb.rUnitGainu4G_low =
(unsigned int)((tempMax * 512 + (CalG >> 1)) / CalG);
pCamCalData->Single2A.S2aAwb.rUnitGainu4B_low =
(unsigned int)((tempMax * 512 + (CalB >> 1)) / CalB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!\n");
pr_debug("Unit R=%d G=%d B=%d!!\n", CalR, CalG, CalB);
}
/* AWB Golden Gain (3100K) */
FacR = FacGr = FacGb = FacG = FacB = 0;
tempMax = 0;
awb_offset = 0x4C;
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
awb_offset, 8, (unsigned char *)&FacGain);
if (read_data_size > 0) {
pr_debug_if(dump_enable, "Read FacGain OK\n");
FacR = FacGain & 0xFFFF;
FacGr = (FacGain >> 16) & 0xFFFF;
FacGb = (FacGain >> 32) & 0xFFFF;
FacG = ((FacGr + FacGb) + 1) >> 1;
FacB = (FacGain >> 48) & 0xFFFF;
if (FacR > FacG)
if (FacR > FacB)
tempMax = FacR;
else
tempMax = FacB;
else
if (FacG > FacB)
tempMax = FacG;
else
tempMax = FacB;
pr_debug_if(dump_enable,
"GoldenR:%d, GoldenG:%d, GoldenB:%d, New Golden Max=%d",
FacR, FacG, FacB, tempMax);
err = CAM_CAL_ERR_NO_ERR;
} else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
pr_debug_err("Read FacGain Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
if (FacGain != 0x0000000000000000 &&
FacGain != 0xFFFFFFFFFFFFFFFF &&
FacR != 0x00000000 &&
FacG != 0x00000000 &&
FacB != 0x00000000) {
pCamCalData->Single2A.S2aAwb.rGoldGainu4R_low =
(unsigned int)((tempMax * 512 + (FacR >> 1)) / FacR);
pCamCalData->Single2A.S2aAwb.rGoldGainu4G_low =
(unsigned int)((tempMax * 512 + (FacG >> 1)) / FacG);
pCamCalData->Single2A.S2aAwb.rGoldGainu4B_low =
(unsigned int)((tempMax * 512 + (FacB >> 1)) / FacB);
} else {
pr_debug("There are something wrong on EEPROM, plz contact module vendor!!");
pr_debug("Golden R=%d G=%d B=%d\n", FacR, FacG, FacB);
}
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("AWB Calibration @3100K\n");
pr_debug("[CalGain] = 0x%llx\n", CalGain);
pr_debug("[FacGain] = 0x%llx\n", FacGain);
pr_debug("[rCalGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4R_low);
pr_debug("[rCalGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4G_low);
pr_debug("[rCalGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rUnitGainu4B_low);
pr_debug("[rFacGain.u4R] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4R_low);
pr_debug("[rFacGain.u4G] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4G_low);
pr_debug("[rFacGain.u4B] = %d\n", pCamCalData->Single2A.S2aAwb.rGoldGainu4B_low);
pr_debug("======================AWB CAM_CAL==================\n");
#endif
}
/* AF Calibration Data*/
if (0x2 & AWBAFConfig) {
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
0x94, 2, (unsigned char *)&AFInf);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
pr_debug_err("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
read_data_size = read_data(pdata, pCamCalData->sensorID, pCamCalData->deviceID,
0x92, 2, (unsigned char *)&AFMacro);
if (read_data_size > 0)
err = CAM_CAL_ERR_NO_ERR;
else {
pCamCalData->Single2A.S2aBitEn = CAM_CAL_NONE_BITEN;
pr_debug_err("Read Failed\n");
show_cmd_error_log(pCamCalData->Command);
}
AFInf = AFInf >> 1;
AFMacro = AFMacro >> 1;
pCamCalData->Single2A.S2aAf[0] = AFInf;
pCamCalData->Single2A.S2aAf[1] = AFMacro;
////Only AF Gathering <////
#ifdef DEBUG_CALIBRATION_LOAD
pr_debug("======================AF CAM_CAL==================\n");
pr_debug("[AFInf] = %d\n", AFInf);
pr_debug("[AFMacro] = %d\n", AFMacro);
pr_debug("======================AF CAM_CAL==================\n");
#endif
}
return err;
}
static unsigned int do_lens_id_brzauwide(struct EEPROM_DRV_FD_DATA *pdata,
unsigned int start_addr, unsigned int block_size, unsigned int *pGetSensorCalData)
{
return do_lens_id_base(pdata, start_addr, block_size, pGetSensorCalData);
}
/*
static unsigned int layout_check_brzauwide(struct EEPROM_DRV_FD_DATA *pdata, unsigned int sensorID, unsigned int *_cfg)
{
unsigned int header_offset = cam_cal_config->layout->header_addr;
unsigned int check_id = 0x00000000;
unsigned int result = CAM_CAL_ERR_NO_DEVICE;
if (cam_cal_config->sensor_id == sensorID)
debug_log("%s sensor_id matched\n", cam_cal_config->name);
else {
debug_log("%s sensor_id not matched\n", cam_cal_config->name);
return result;
}
if (read_data_region(pdata, (u8 *)&check_id, header_offset, 4) != 4) {
debug_log("header_id read failed\n");
return result;
}
if (check_id == 0x016B012B || check_id == 0x016d009a) { // hearder id on OTP guide
debug_log("header_id matched 0x%08x\n", check_id);
printk("brzaheader_id wide matched 0x%08x\n", check_id);
result = CAM_CAL_ERR_NO_ERR;
} else{
debug_log("header_id not matched 0x%08x\n", check_id);
printk("brzaheader_id wide not matched 0x%08x\n", check_id);
}
return result;
}*/

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